Paper Abstract and Keywords |
Presentation |
2010-04-22 11:15
A 40-nm Low-power SRAM with Multi-stage Replica-Bitline Scheme for Reducing Timing Variation Shigenobu Komatsu, Masanao Yamaoka (HITACHI), Masao Morimoto, Noriaki Maeda, Yasuhisa Shimazaki (Renesas Technology Corp.), Kenichi Osada (HITACHI) ICD2010-4 Link to ES Tech. Rep. Archives: ICD2010-4 |
Abstract |
(in Japanese) |
(See Japanese page) |
(in English) |
A multi-stage replica bitline scheme for reducing access time by suppressing enable timing variation of a sense amplifier was developed. Applied to a 288-kbit SRAM of the 40nm process node, this scheme achieves 6.1% access time reduction by reducing the sense-amplifier timing variation by 43%. |
Keyword |
(in Japanese) |
(See Japanese page) |
(in English) |
SRAM / Replica-bitline / Random Variation / / / / / |
Reference Info. |
IEICE Tech. Rep., vol. 110, no. 9, ICD2010-4, pp. 17-21, April 2010. |
Paper # |
ICD2010-4 |
Date of Issue |
2010-04-15 (ICD) |
ISSN |
Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 |
Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) |
Download PDF |
ICD2010-4 Link to ES Tech. Rep. Archives: ICD2010-4 |
Conference Information |
Committee |
ICD |
Conference Date |
2010-04-22 - 2010-04-23 |
Place (in Japanese) |
(See Japanese page) |
Place (in English) |
Shonan Institute of Tech. |
Topics (in Japanese) |
(See Japanese page) |
Topics (in English) |
Memory Device Technologies |
Paper Information |
Registration To |
ICD |
Conference Code |
2010-04-ICD |
Language |
Japanese |
Title (in Japanese) |
(See Japanese page) |
Sub Title (in Japanese) |
(See Japanese page) |
Title (in English) |
A 40-nm Low-power SRAM with Multi-stage Replica-Bitline Scheme for Reducing Timing Variation |
Sub Title (in English) |
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Keyword(1) |
SRAM |
Keyword(2) |
Replica-bitline |
Keyword(3) |
Random Variation |
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1st Author's Name |
Shigenobu Komatsu |
1st Author's Affiliation |
HITACHI, Ltd. (HITACHI) |
2nd Author's Name |
Masanao Yamaoka |
2nd Author's Affiliation |
HITACHI, Ltd. (HITACHI) |
3rd Author's Name |
Masao Morimoto |
3rd Author's Affiliation |
Renesas Technology Corp. (Renesas Technology Corp.) |
4th Author's Name |
Noriaki Maeda |
4th Author's Affiliation |
Renesas Technology Corp. (Renesas Technology Corp.) |
5th Author's Name |
Yasuhisa Shimazaki |
5th Author's Affiliation |
Renesas Technology Corp. (Renesas Technology Corp.) |
6th Author's Name |
Kenichi Osada |
6th Author's Affiliation |
HITACHI, Ltd. (HITACHI) |
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Speaker |
Author-1 |
Date Time |
2010-04-22 11:15:00 |
Presentation Time |
25 minutes |
Registration for |
ICD |
Paper # |
ICD2010-4 |
Volume (vol) |
vol.110 |
Number (no) |
no.9 |
Page |
pp.17-21 |
#Pages |
5 |
Date of Issue |
2010-04-15 (ICD) |
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