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Paper Abstract and Keywords
Presentation 2010-04-22 15:20
Fabrication of a Nonvolatile Lookup-Table Circuit Chip Using Magneto/Semiconductor-Hybrid Structure for an Immediate-Power-Up Field Programmable Gate Array
Daisuke Suzuki, Masanori Natsui, Shoji Ikeda (Tohoku Univ.), Haruhiro Hasegawa, Katsuya Miura, Jun Hayakawa (ARL, Hitachi, Ltd.), Tetsuo Endoh, Hideo Ohno, Takahiro Hanyu (Tohoku Univ.) ICD2010-9 Link to ES Tech. Rep. Archives: ICD2010-9
Abstract (in Japanese) (See Japanese page) 
(in English) This paper presents a nonvolatile LUT (Lookup-Table) circuit in FPGA (Field-Programmable Gate Array) using a MTJ (Magnetic Tunnel Junction) device-based logic technology. To utilize a capability of MTJ devices, the combinational logic circuitry is implemented based on differential current-mode logic methodology. Since the circuit performs current-mode logic operations under low voltage swing, the variation of current flows through MTJ devices can be applied as logic signals directly with no signal amplification. It results in a compact circuit implementation.
The proposed LUT circuit fabricated by a 0.14$\mu$m CMOS/MTJ-hybrid process achieves area reduction by 2/3 compared to a conventional SRAM-based one, and complete elimination of standby power dissipation.
Keyword (in Japanese) (See Japanese page) 
(in English) MTJ device / FPGA / LUT / Logic-in-memory circuit / Current-mode-logic / / /  
Reference Info. IEICE Tech. Rep., vol. 110, no. 9, ICD2010-9, pp. 47-52, April 2010.
Paper # ICD2010-9 
Date of Issue 2010-04-15 (ICD) 
ISSN Print edition: ISSN 0913-5685    Online edition: ISSN 2432-6380
Copyright
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All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF ICD2010-9 Link to ES Tech. Rep. Archives: ICD2010-9

Conference Information
Committee ICD  
Conference Date 2010-04-22 - 2010-04-23 
Place (in Japanese) (See Japanese page) 
Place (in English) Shonan Institute of Tech. 
Topics (in Japanese) (See Japanese page) 
Topics (in English) Memory Device Technologies 
Paper Information
Registration To ICD 
Conference Code 2010-04-ICD 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) Fabrication of a Nonvolatile Lookup-Table Circuit Chip Using Magneto/Semiconductor-Hybrid Structure for an Immediate-Power-Up Field Programmable Gate Array 
Sub Title (in English)  
Keyword(1) MTJ device  
Keyword(2) FPGA  
Keyword(3) LUT  
Keyword(4) Logic-in-memory circuit  
Keyword(5) Current-mode-logic  
Keyword(6)  
Keyword(7)  
Keyword(8)  
1st Author's Name Daisuke Suzuki  
1st Author's Affiliation Tohoku University (Tohoku Univ.)
2nd Author's Name Masanori Natsui  
2nd Author's Affiliation Tohoku University (Tohoku Univ.)
3rd Author's Name Shoji Ikeda  
3rd Author's Affiliation Tohoku University (Tohoku Univ.)
4th Author's Name Haruhiro Hasegawa  
4th Author's Affiliation Advanced Research Laboratory, Hitachi, Ltd. (ARL, Hitachi, Ltd.)
5th Author's Name Katsuya Miura  
5th Author's Affiliation Advanced Research Laboratory, Hitachi, Ltd. (ARL, Hitachi, Ltd.)
6th Author's Name Jun Hayakawa  
6th Author's Affiliation Advanced Research Laboratory, Hitachi, Ltd. (ARL, Hitachi, Ltd.)
7th Author's Name Tetsuo Endoh  
7th Author's Affiliation Tohoku University (Tohoku Univ.)
8th Author's Name Hideo Ohno  
8th Author's Affiliation Tohoku University (Tohoku Univ.)
9th Author's Name Takahiro Hanyu  
9th Author's Affiliation Tohoku University (Tohoku Univ.)
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Speaker Author-1 
Date Time 2010-04-22 15:20:00 
Presentation Time 25 minutes 
Registration for ICD 
Paper # ICD2010-9 
Volume (vol) vol.110 
Number (no) no.9 
Page pp.47-52 
#Pages
Date of Issue 2010-04-15 (ICD) 


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