Paper Abstract and Keywords |
Presentation |
2010-03-28 11:15
Design and Evaluation of An Instruction Scheduler for FU Array Processor Kazuhiro Yoshimura, Munehisa Agari, Takashi Nakada, Yasuhiko Nakashima (NAIST) CPSY2009-94 DC2009-91 |
Abstract |
(in Japanese) |
(See Japanese page) |
(in English) |
Recently, we have proposed Linear Array Pipeline Processor (LAPP) that improves energy efficiency for various workloads like image processing and maintains programmability by working on VLIW codes. In this paper, we proposed an instruction scheduler for LAPP to fully exploit the array execution functional units (FUs) and bypass networks by mapping the VLIW codes into the FUs dynamically. The dynamic scheduling can be finished within multi-cycles during a data prefetching before the FUs work concurrently. According to its design with HDL, the proposed scheduler has become the circuit area to 43% and the delay to 70% compared to a straightforward model. The scheduling also does not have any critical path in an FU array processor with the small footprint. |
Keyword |
(in Japanese) |
(See Japanese page) |
(in English) |
instruction scheduling / array execution units / reconfigurable architecture / / / / / |
Reference Info. |
IEICE Tech. Rep., vol. 109, no. 474, CPSY2009-94, pp. 511-516, March 2010. |
Paper # |
CPSY2009-94 |
Date of Issue |
2010-03-19 (CPSY, DC) |
ISSN |
Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 |
Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) |
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CPSY2009-94 DC2009-91 |
Conference Information |
Committee |
CPSY DC IPSJ-SLDM IPSJ-EMB IPSJ-UBI IPSJ-MBL |
Conference Date |
2010-03-26 - 2010-03-28 |
Place (in Japanese) |
(See Japanese page) |
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Paper Information |
Registration To |
CPSY |
Conference Code |
2010-03-CPSY-DC |
Language |
Japanese |
Title (in Japanese) |
(See Japanese page) |
Sub Title (in Japanese) |
(See Japanese page) |
Title (in English) |
Design and Evaluation of An Instruction Scheduler for FU Array Processor |
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Keyword(1) |
instruction scheduling |
Keyword(2) |
array execution units |
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reconfigurable architecture |
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1st Author's Name |
Kazuhiro Yoshimura |
1st Author's Affiliation |
Nara Institute of Science and Technology (NAIST) |
2nd Author's Name |
Munehisa Agari |
2nd Author's Affiliation |
Nara Institute of Science and Technology (NAIST) |
3rd Author's Name |
Takashi Nakada |
3rd Author's Affiliation |
Nara Institute of Science and Technology (NAIST) |
4th Author's Name |
Yasuhiko Nakashima |
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Nara Institute of Science and Technology (NAIST) |
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Speaker |
Author-1 |
Date Time |
2010-03-28 11:15:00 |
Presentation Time |
20 minutes |
Registration for |
CPSY |
Paper # |
CPSY2009-94, DC2009-91 |
Volume (vol) |
vol.109 |
Number (no) |
no.474(CPSY), no.475(DC) |
Page |
pp.511-516 |
#Pages |
6 |
Date of Issue |
2010-03-19 (CPSY, DC) |
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