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Paper Abstract and Keywords
Presentation 2010-03-12 10:00
Software Development Tool Generation Method Suitable for Instruction Set Extension of Embedded Processors
Takahiro Kumura (NEC/Osaka Univ.), Soichiro Taga, Nagisa Ishiura (Kwansei Gakuin Univ.), Yoshinori Takeuchi, Masaharu Imai (Osaka Univ.) VLD2009-120
Abstract (in Japanese) (See Japanese page) 
(in English) This paper proposes a method of software development tool generation suitable for instruction set extension of existing embedded processors. The key idea in the proposed method is to enhance a base processor's toolchain by adding plugins, which are software components that handle additional instructions and registers. The proposed method can generate a compiler, assembler, disassebler, and instruction set simulator. Generated compilers with the plugins provide intrinsic functions that are translated directly into the new instructions. To demonstrate that the proposed method works effectively, this paper presents an experimental result of the proposed method in the study of adding SIMD instructions to the embedded microprocessor V850. In the experiment, by using intrinsic functions, the compiler generated good code with only 7\% increase in the number of instructions against the hand-optimized assembly codes.
Keyword (in Japanese) (See Japanese page) 
(in English) Architecture description language / Tool generation / Plug-in / Intrinsic function / / / /  
Reference Info. IEICE Tech. Rep., vol. 109, no. 462, VLD2009-120, pp. 127-132, March 2010.
Paper # VLD2009-120 
Date of Issue 2010-03-03 (VLD) 
ISSN Print edition: ISSN 0913-5685  Online edition: ISSN 2432-6380
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (No. 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF VLD2009-120

Conference Information
Committee VLD  
Conference Date 2010-03-10 - 2010-03-12 
Place (in Japanese) (See Japanese page) 
Place (in English)  
Topics (in Japanese) (See Japanese page) 
Topics (in English) Design Technology for System-on-Silicon 
Paper Information
Registration To VLD 
Conference Code 2010-03-VLD 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) Software Development Tool Generation Method Suitable for Instruction Set Extension of Embedded Processors 
Sub Title (in English)  
Keyword(1) Architecture description language  
Keyword(2) Tool generation  
Keyword(3) Plug-in  
Keyword(4) Intrinsic function  
1st Author's Name Takahiro Kumura  
1st Author's Affiliation NEC Corporation/Osaka University (NEC/Osaka Univ.)
2nd Author's Name Soichiro Taga  
2nd Author's Affiliation Kwansei Gakuin University (Kwansei Gakuin Univ.)
3rd Author's Name Nagisa Ishiura  
3rd Author's Affiliation Kwansei Gakuin University (Kwansei Gakuin Univ.)
4th Author's Name Yoshinori Takeuchi  
4th Author's Affiliation Osaka University (Osaka Univ.)
5th Author's Name Masaharu Imai  
5th Author's Affiliation Osaka University (Osaka Univ.)
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Date Time 2010-03-12 10:00:00 
Presentation Time 25 
Registration for VLD 
Paper # IEICE-VLD2009-120 
Volume (vol) IEICE-109 
Number (no) no.462 
Page pp.127-132 
#Pages IEICE-6 
Date of Issue IEICE-VLD-2010-03-03 

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