Paper Abstract and Keywords |
Presentation |
2010-03-11 15:00
Fast Estimation Method of Peak Power considered Input Vector and Inner State of a Circuit Nobuyoshi Takahashi (Tokyo Inst. of Tech.), Yoichi Tomioka (Tokyo Univ. of Agriculture and Tech.), Yukihide Kohira (The Univ. of Aizu), Atsushi Takahashi (Osaka Univ.) VLD2009-115 |
Abstract |
(in Japanese) |
(See Japanese page) |
(in English) |
The peak power of a clock synchronous circuit is requested to be small to reduce the influence on circuit performance and environment. Though a circuit whose peak power is small is obtained by general-synchronous framework, the peak power of a circuit should be accurately estimated in short time. In our previous work, NVS method that generates a set of pairs of input vectors that have potential to achieve higher peak power was proposed. NVS method specifies the time when the power consumption of a circuit by a given pair of input vectors is maximum, then generates a set of pairs of input vectors such that the power consumption of a circuit at the specified time by each of them is higher than the given pair of input vectors. In this paper, we confirm that NVS method generates a set of pairs of input vectors in short time, and that by circuit simulation an appropriate pair of input vectors to estimate peak power is obtained by NVS method. |
Keyword |
(in Japanese) |
(See Japanese page) |
(in English) |
Clock Synchronous Circuit / Peak Power Estimation / Input Vector / / / / / |
Reference Info. |
IEICE Tech. Rep., vol. 109, no. 462, VLD2009-115, pp. 97-102, March 2010. |
Paper # |
VLD2009-115 |
Date of Issue |
2010-03-03 (VLD) |
ISSN |
Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 |
Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) |
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VLD2009-115 |
Conference Information |
Committee |
VLD |
Conference Date |
2010-03-10 - 2010-03-12 |
Place (in Japanese) |
(See Japanese page) |
Place (in English) |
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Topics (in Japanese) |
(See Japanese page) |
Topics (in English) |
Design Technology for System-on-Silicon |
Paper Information |
Registration To |
VLD |
Conference Code |
2010-03-VLD |
Language |
Japanese |
Title (in Japanese) |
(See Japanese page) |
Sub Title (in Japanese) |
(See Japanese page) |
Title (in English) |
Fast Estimation Method of Peak Power considered Input Vector and Inner State of a Circuit |
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Keyword(1) |
Clock Synchronous Circuit |
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Peak Power Estimation |
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Input Vector |
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1st Author's Name |
Nobuyoshi Takahashi |
1st Author's Affiliation |
Tokyo Institute of Technology (Tokyo Inst. of Tech.) |
2nd Author's Name |
Yoichi Tomioka |
2nd Author's Affiliation |
Tokyo University of Agriculture and Technology (Tokyo Univ. of Agriculture and Tech.) |
3rd Author's Name |
Yukihide Kohira |
3rd Author's Affiliation |
The University of Aizu (The Univ. of Aizu) |
4th Author's Name |
Atsushi Takahashi |
4th Author's Affiliation |
Osaka University (Osaka Univ.) |
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Speaker |
Author-1 |
Date Time |
2010-03-11 15:00:00 |
Presentation Time |
25 minutes |
Registration for |
VLD |
Paper # |
VLD2009-115 |
Volume (vol) |
vol.109 |
Number (no) |
no.462 |
Page |
pp.97-102 |
#Pages |
6 |
Date of Issue |
2010-03-03 (VLD) |
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