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| Presentation | 2010-03-11 10:25 Examination of the best basic logic gate architecture for Via programmable logic device Ryohei Hori, Yuuichi Kokushou, Tomohiro Nishimoto, Shouta Yamada, Naoyuki Yoshida, Naoki Matsumoto, Takeshi Fujino (Ritsumei Univ.), Masaya Yoshikawa (Meijo Univ.)  VLD2009-108 |
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| Abstract | (in Japanese) | (See Japanese page) |
| (in English) | The structured ASIC on which the logic can be customized with a few mask layers, have been studied in order to reduce initial development cost including mask cost. We have been developed via-programmable logic device named VPEX, which can be programmed by 2 via layers. The logic element (LE) of VPEX consists of complex-gate type EXOR gate and NOT gate. In addition to all 2-input logic functions, some 3-input logic functions such as AOI and multiplexer can be programmed by a single LE. The DFF can be configured by two LEs in the VPEX. Compared with other LEs such as 2-input LUT or SOP, the area and the delay of VPEX LE is as small as that of other LE, It is noted that the power consumption of VPEX is less than half of other 2-input LEs. In this paper, we report the logic-synthesized results of several benchmark circuits, in order to evaluate the area and the speed performance of VPEX |
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| Keyword | (in Japanese) | (See Japanese page) |
| (in English) | Via-programmable logic / EB direct writing / Exclusive-OR / structured ASIC / / / / | |
| Reference Info. | IEICE Tech. Rep., vol. 109, no. 462, VLD2009-108, pp. 55-60, March 2010. | |
| Paper # | VLD2009-108 | |
| Date of Issue | 2010-03-03 (VLD) | |
| ISSN | Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 | |
| Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) | |
| Download PDF | VLD2009-108 |
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| Conference Information | |
| Committee | VLD |
| Conference Date | 2010-03-10 - 2010-03-12 |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | Design Technology for System-on-Silicon |
| Paper Information | |
| Registration To | VLD |
| Conference Code | 2010-03-VLD |
| Language | Japanese |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Examination of the best basic logic gate architecture for Via programmable logic device |
| Sub Title (in English) | |
| Keyword(1) | Via-programmable logic |
| Keyword(2) | EB direct writing |
| Keyword(3) | Exclusive-OR |
| Keyword(4) | structured ASIC |
| Keyword(5) | |
| Keyword(6) | |
| Keyword(7) | |
| Keyword(8) | |
| 1st Author's Name | Ryohei Hori |
| 1st Author's Affiliation | Ritsumeikan University (Ritsumei Univ.) |
| 2nd Author's Name | Yuuichi Kokushou |
| 2nd Author's Affiliation | Ritsumeikan University (Ritsumei Univ.) |
| 3rd Author's Name | Tomohiro Nishimoto |
| 3rd Author's Affiliation | Ritsumeikan University (Ritsumei Univ.) |
| 4th Author's Name | Shouta Yamada |
| 4th Author's Affiliation | Ritsumeikan University (Ritsumei Univ.) |
| 5th Author's Name | Naoyuki Yoshida |
| 5th Author's Affiliation | Ritsumeikan University (Ritsumei Univ.) |
| 6th Author's Name | Naoki Matsumoto |
| 6th Author's Affiliation | Ritsumeikan University (Ritsumei Univ.) |
| 7th Author's Name | Takeshi Fujino |
| 7th Author's Affiliation | Ritsumeikan University (Ritsumei Univ.) |
| 8th Author's Name | Masaya Yoshikawa |
| 8th Author's Affiliation | Meijo University (Meijo Univ.) |
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| Speaker | Author-1 |
| Date Time | 2010-03-11 10:25:00 |
| Presentation Time | 25 minutes |
| Registration for | VLD |
| Paper # | VLD2009-108 |
| Volume (vol) | vol.109 |
| Number (no) | no.462 |
| Page | pp.55-60 |
| #Pages | 6 |
| Date of Issue | 2010-03-03 (VLD) |
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