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Paper Abstract and Keywords
Presentation 2010-03-10 15:25
Generation Mechanism of SEU and MCU Caused by Parasitic Lateral Bipolar Transitstors
Chikara Hamanaka (Kyoto Institute of Tech.), Jun Furuta, Hiroaki Makino (Kyoto Univ.), Kazutoshi Kobayashi (Kyoto Institute of Tech.), Hidetoshi Onodera (Kyoto Univ./JST, CREST) VLD2009-103
Abstract (in Japanese) (See Japanese page) 
(in English) Tolerance for soft-error decreases as integration advances. SEU(Single Event Upset), flipping one bit
and MCU(Multi-Cell Upset), flipping two or more bits at the same time, becomes a problem. It is assumed that
MCU is caused by the charge distribution generated by the neutron or alpha particles, etc. Recently, it is said that
the effect of a parasitic bipolar transistor whose base is the well or the substrate is a dominant factor on MCU.
In this paper, the substrate bipolar transistor and the substrate resistance modeled from the measurement results
are embedded into SPICE simulation, and it examines how to generate SEU and MCU. We examined SRAM type
latches composed of cross-coupled inverters and ordinal latches by three-state inverters in D-FF. SEU rate is almost
constant regardless of the distance from the substrate tap, while the further from substrate tap, the easier MCU
occurs.
Keyword (in Japanese) (See Japanese page) 
(in English) Soft Error / SEU(Single Event Upset) / MCU(Multi-Cell Upset) / Substrate Bipolar Transistor / LSI / CMOS / /  
Reference Info. IEICE Tech. Rep., vol. 109, no. 462, VLD2009-103, pp. 25-30, March 2010.
Paper # VLD2009-103 
Date of Issue 2010-03-03 (VLD) 
ISSN Print edition: ISSN 0913-5685    Online edition: ISSN 2432-6380
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Download PDF VLD2009-103

Conference Information
Committee VLD  
Conference Date 2010-03-10 - 2010-03-12 
Place (in Japanese) (See Japanese page) 
Place (in English)  
Topics (in Japanese) (See Japanese page) 
Topics (in English) Design Technology for System-on-Silicon 
Paper Information
Registration To VLD 
Conference Code 2010-03-VLD 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) Generation Mechanism of SEU and MCU Caused by Parasitic Lateral Bipolar Transitstors 
Sub Title (in English)  
Keyword(1) Soft Error  
Keyword(2) SEU(Single Event Upset)  
Keyword(3) MCU(Multi-Cell Upset)  
Keyword(4) Substrate Bipolar Transistor  
Keyword(5) LSI  
Keyword(6) CMOS  
Keyword(7)  
Keyword(8)  
1st Author's Name Chikara Hamanaka  
1st Author's Affiliation Kyoto Institute of Technology (Kyoto Institute of Tech.)
2nd Author's Name Jun Furuta  
2nd Author's Affiliation Kyoto University (Kyoto Univ.)
3rd Author's Name Hiroaki Makino  
3rd Author's Affiliation Kyoto University (Kyoto Univ.)
4th Author's Name Kazutoshi Kobayashi  
4th Author's Affiliation Kyoto Institute of Technology (Kyoto Institute of Tech.)
5th Author's Name Hidetoshi Onodera  
5th Author's Affiliation Kyoto University/JST, CREST (Kyoto Univ./JST, CREST)
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Speaker Author-1 
Date Time 2010-03-10 15:25:00 
Presentation Time 25 minutes 
Registration for VLD 
Paper # VLD2009-103 
Volume (vol) vol.109 
Number (no) no.462 
Page pp.25-30 
#Pages
Date of Issue 2010-03-03 (VLD) 


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