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Paper Abstract and Keywords
Presentation 2010-03-05 15:50
A PLL Synthesizer Composed of Parallel Dual Modulus Prescaler with a step size of 0.5
Hideyuki Nakamizo, Kenichi Tajima, Ryoji Hayashi (Mitsubishi Electric Corp.), Toshiya Uozumi (Renesas Technology Corp.) MW2009-209 Link to ES Tech. Rep. Archives: MW2009-209
Abstract (in Japanese) (See Japanese page) 
(in English) By reducing the step size of the programmable frequency divider in Fractional-N PLL from 1 to 0.5, the phase noise contributed by the fractional division is reduced by 6dB.
This paper shows a PLL synthesizer composed of a pulse swallow programmable divider with the division step size is 0.5.
To realize the division step size of 0.5, we propose a parallel dual modulus prescaler architecture with a division factor P or P+0.5.
The PLL synthesizer with the proposed parallel dual modulus prescaler is implemented in a 0.13-μm CMOS process and confirmed the characteristics at 5GHz.
Keyword (in Japanese) (See Japanese page) 
(in English) Phase Lock loop / Fractional-N / Divider / Dual Modulus Prescaler / Phase Noise / / /  
Reference Info. IEICE Tech. Rep., vol. 109, no. 431, MW2009-209, pp. 175-178, March 2010.
Paper # MW2009-209 
Date of Issue 2010-02-25 (MW) 
ISSN Print edition: ISSN 0913-5685    Online edition: ISSN 2432-6380
Copyright
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reproduction
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF MW2009-209 Link to ES Tech. Rep. Archives: MW2009-209

Conference Information
Committee MW  
Conference Date 2010-03-04 - 2010-03-05 
Place (in Japanese) (See Japanese page) 
Place (in English) Ryukoku Univ. 
Topics (in Japanese) (See Japanese page) 
Topics (in English) Microwave Technologies 
Paper Information
Registration To MW 
Conference Code 2010-03-MW 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) A PLL Synthesizer Composed of Parallel Dual Modulus Prescaler with a step size of 0.5 
Sub Title (in English)  
Keyword(1) Phase Lock loop  
Keyword(2) Fractional-N  
Keyword(3) Divider  
Keyword(4) Dual Modulus Prescaler  
Keyword(5) Phase Noise  
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1st Author's Name Hideyuki Nakamizo  
1st Author's Affiliation Mitsubishi Electric Corporation (Mitsubishi Electric Corp.)
2nd Author's Name Kenichi Tajima  
2nd Author's Affiliation Mitsubishi Electric Corporation (Mitsubishi Electric Corp.)
3rd Author's Name Ryoji Hayashi  
3rd Author's Affiliation Mitsubishi Electric Corporation (Mitsubishi Electric Corp.)
4th Author's Name Toshiya Uozumi  
4th Author's Affiliation Renesas Technology Corporation (Renesas Technology Corp.)
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Speaker Author-1 
Date Time 2010-03-05 15:50:00 
Presentation Time 25 minutes 
Registration for MW 
Paper # MW2009-209 
Volume (vol) vol.109 
Number (no) no.431 
Page pp.175-178 
#Pages
Date of Issue 2010-02-25 (MW) 


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