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| Presentation | 2010-02-15 13:20 Reduction of execution times and areas for delay measurement by subtraction Toru Tanabe, Hirohisa Minato, Kentaroh Katoh, Kazuteru Namba, Hideo Ito (Chiba Univ.)  DC2009-71 |
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| Abstract | (in Japanese) | (See Japanese page) |
| (in English) | Since VLSI is in nanoscase size, high density and high speed in recent years, small-delay defects which change propagation time of a signal in the circuit become a serious problem. The techniques for measurement of the actual delay time of a path in the circuit are useful for detection of small-delay defects during manufacturing testing. This paper presents a method to reduce the execution times and the areas for the method of a delay measurement by using subtraction. Evaluation shows that the areas overhead and the execution times for the proposed method are about 20~35% smaller and 45~65% shorter than those for the conventional method respectively. | |
| Keyword | (in Japanese) | (See Japanese page) |
| (in English) | VLSI / delay fault / testing / scan path / small-delay defect / measurement / / | |
| Reference Info. | IEICE Tech. Rep., vol. 109, no. 416, DC2009-71, pp. 39-44, Feb. 2010. | |
| Paper # | DC2009-71 | |
| Date of Issue | 2010-02-08 (DC) | |
| ISSN | Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 | |
| Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) | |
| Download PDF | DC2009-71 |
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| Conference Information | |
| Committee | DC |
| Conference Date | 2010-02-15 - 2010-02-15 |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | Kikai-Shinko-Kaikan Bldg. |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
| Paper Information | |
| Registration To | DC |
| Conference Code | 2010-02-DC |
| Language | Japanese |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Reduction of execution times and areas for delay measurement by subtraction |
| Sub Title (in English) | |
| Keyword(1) | VLSI |
| Keyword(2) | delay fault |
| Keyword(3) | testing |
| Keyword(4) | scan path |
| Keyword(5) | small-delay defect |
| Keyword(6) | measurement |
| Keyword(7) | |
| Keyword(8) | |
| 1st Author's Name | Toru Tanabe |
| 1st Author's Affiliation | Chiba University (Chiba Univ.) |
| 2nd Author's Name | Hirohisa Minato |
| 2nd Author's Affiliation | Chiba University (Chiba Univ.) |
| 3rd Author's Name | Kentaroh Katoh |
| 3rd Author's Affiliation | Chiba University (Chiba Univ.) |
| 4th Author's Name | Kazuteru Namba |
| 4th Author's Affiliation | Chiba University (Chiba Univ.) |
| 5th Author's Name | Hideo Ito |
| 5th Author's Affiliation | Chiba University (Chiba Univ.) |
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| Speaker | Author-1 |
| Date Time | 2010-02-15 13:20:00 |
| Presentation Time | 25 minutes |
| Registration for | DC |
| Paper # | DC2009-71 |
| Volume (vol) | vol.109 |
| Number (no) | no.416 |
| Page | pp.39-44 |
| #Pages | 6 |
| Date of Issue | 2010-02-08 (DC) |
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