Paper Abstract and Keywords |
Presentation |
2010-02-15 10:25
Modeling resistive open faults and generating their tests Hiroshi Takahashi, Yoshinobu Higami, Yuta Shudo, Yuji Takamune, Yuzo Takamatsu (Ehime Univ.), Toshiyuki Tsutsumi, Koji Yamazaki (Meiji Univ.), Hiroyuki Yotsuyanagi, Masaki Hashizume (Univ. of Tokushima) DC2009-68 |
Abstract |
(in Japanese) |
(See Japanese page) |
(in English) |
In order to solve the problem of signal integrity, we propose an extended delay fault model for modeling a resistive open fault.
We use the three-dimensional electromagnetic software to analyze the behavior of a line with the resistive open.
Under the extended delay fault model proposed in this paper, the size of the additional delay is depended on the signal transitions at the adjacent lines that are assigned by the test-pair.
Under the launch on capture (LOC) test, we propose a method for generating the test-pairs for the resistive open faults by using the transition fault tests with don't cares.
We demonstrated the experimental results to show that the proposed method is able to generate the test-pair for resistive open faults that cannot be detected by the given test-pairs for the transition faults. |
Keyword |
(in Japanese) |
(See Japanese page) |
(in English) |
resistive open fault / test pattern generation / extended delay fault model / adjacent lines / / / / |
Reference Info. |
IEICE Tech. Rep., vol. 109, no. 416, DC2009-68, pp. 19-24, Feb. 2010. |
Paper # |
DC2009-68 |
Date of Issue |
2010-02-08 (DC) |
ISSN |
Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 |
Copyright and reproduction |
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DC2009-68 |
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