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| Presentation | 2010-02-15 14:35 Seed Selection for High Quality Delay Fault Test in BIST Akira Taketani, Tomokazu Yoneda, Michiko Inoue, Hideo Fujiwara (Nara Inst. of Sci and Tech.)  DC2009-74 |
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| Abstract | (in Japanese) | (See Japanese page) |
| (in English) | In this paper, we target a scan BIST architecture that consists of LFSR, phase shifter and MISR, and propose a method to select seeds for high quality delay testing under a constraint on the test data volume. In the proposed method, we first generate a set of test cubes for small delay defects and convert it into a set of seeds. Then, we efficiently select a seed set with high delay quality in terms of SDQL. Experimental results for ITC'99 benchmark circuits show that the proposed method can obtain a high quality seed set with reasonable computation time. | |
| Keyword | (in Japanese) | (See Japanese page) |
| (in English) | BIST / seed selection / delay test / SDQM / / / / | |
| Reference Info. | IEICE Tech. Rep., vol. 109, no. 416, DC2009-74, pp. 57-62, Feb. 2010. | |
| Paper # | DC2009-74 | |
| Date of Issue | 2010-02-08 (DC) | |
| ISSN | Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 | |
| Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) | |
| Download PDF | DC2009-74 |
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| Conference Information | |
| Committee | DC |
| Conference Date | 2010-02-15 - 2010-02-15 |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | Kikai-Shinko-Kaikan Bldg. |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
| Paper Information | |
| Registration To | DC |
| Conference Code | 2010-02-DC |
| Language | Japanese |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Seed Selection for High Quality Delay Fault Test in BIST |
| Sub Title (in English) | |
| Keyword(1) | BIST |
| Keyword(2) | seed selection |
| Keyword(3) | delay test |
| Keyword(4) | SDQM |
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| 1st Author's Name | Akira Taketani |
| 1st Author's Affiliation | Graduate School of Information Science, Nara Institute of Science and Technology (Nara Inst. of Sci and Tech.) |
| 2nd Author's Name | Tomokazu Yoneda |
| 2nd Author's Affiliation | Graduate School of Information Science, Nara Institute of Science and Technology (Nara Inst. of Sci and Tech.) |
| 3rd Author's Name | Michiko Inoue |
| 3rd Author's Affiliation | Graduate School of Information Science, Nara Institute of Science and Technology (Nara Inst. of Sci and Tech.) |
| 4th Author's Name | Hideo Fujiwara |
| 4th Author's Affiliation | Graduate School of Information Science, Nara Institute of Science and Technology (Nara Inst. of Sci and Tech.) |
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| Speaker | Author-1 |
| Date Time | 2010-02-15 14:35:00 |
| Presentation Time | 25 minutes |
| Registration for | DC |
| Paper # | DC2009-74 |
| Volume (vol) | vol.109 |
| Number (no) | no.416 |
| Page | pp.57-62 |
| #Pages | 6 |
| Date of Issue | 2010-02-08 (DC) |
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