IEICE Technical Committee Submission System
Conference Paper's Information
Online Proceedings
[Sign in]
Tech. Rep. Archives
 Go Top Page Go Previous   [Japanese] / [English] 

Paper Abstract and Keywords
Presentation 2010-01-29 13:25
Developing an Architecture for a Single-Flux Quantum Based Reconfigurable Accelerator
Farhad Mehdipour (Kyushu Univ.), Hiroaki Honda (ISIT), Hiroshi Kataoka, Koji Inoue, Kazuaki Murakami (Kyushu Univ.) ICD2009-111 Link to ES Tech. Rep. Archives: ICD2009-111
Abstract (in Japanese) (See Japanese page) 
(in English) As a solution to gain high performance computation, a large scale reconfigurable data-path (LSRDP) processor is
introduced in this paper. LSRDP is implemented by virtue of
single-flux quantum circuits and integrated to a general
purpose processor to accelerate the execution of data flow
graphs (DFGs) extracted from scientific applications. Design
procedure of the LSRDP and particularly the process of
mapping DFGs onto the LSRDP are discussed and our
techniques for reducing the area of accelerator will be
presented as well.
Keyword (in Japanese) (See Japanese page) 
(in English) Reconfigurable accelerator / Single-flux quantum circuit / data flow graph / placement and routing / / / /  
Reference Info. IEICE Tech. Rep., vol. 109, no. 405, ICD2009-111, pp. 99-104, Jan. 2010.
Paper # ICD2009-111 
Date of Issue 2010-01-21 (ICD) 
ISSN Print edition: ISSN 0913-5685  Online edition: ISSN 2432-6380
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF ICD2009-111 Link to ES Tech. Rep. Archives: ICD2009-111

Conference Information
Conference Date 2010-01-28 - 2010-01-29 
Place (in Japanese) (See Japanese page) 
Place (in English) T.B.D. 
Topics (in Japanese) (See Japanese page) 
Topics (in English)  
Paper Information
Registration To ICD 
Conference Code 2010-01-ICD-ARC-EMB 
Language English 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) Developing an Architecture for a Single-Flux Quantum Based Reconfigurable Accelerator 
Sub Title (in English)  
Keyword(1) Reconfigurable accelerator  
Keyword(2) Single-flux quantum circuit  
Keyword(3) data flow graph  
Keyword(4) placement and routing  
1st Author's Name Farhad Mehdipour  
1st Author's Affiliation Kyushu University (Kyushu Univ.)
2nd Author's Name Hiroaki Honda  
2nd Author's Affiliation Institute of Systems, Information Technologies and Nanotechnologies (ISIT)
3rd Author's Name Hiroshi Kataoka  
3rd Author's Affiliation Kyushu University (Kyushu Univ.)
4th Author's Name Koji Inoue  
4th Author's Affiliation Kyushu University (Kyushu Univ.)
5th Author's Name Kazuaki Murakami  
5th Author's Affiliation Kyushu University (Kyushu Univ.)
6th Author's Name  
6th Author's Affiliation ()
7th Author's Name  
7th Author's Affiliation ()
8th Author's Name  
8th Author's Affiliation ()
9th Author's Name  
9th Author's Affiliation ()
10th Author's Name  
10th Author's Affiliation ()
11th Author's Name  
11th Author's Affiliation ()
12th Author's Name  
12th Author's Affiliation ()
13th Author's Name  
13th Author's Affiliation ()
14th Author's Name  
14th Author's Affiliation ()
15th Author's Name  
15th Author's Affiliation ()
16th Author's Name  
16th Author's Affiliation ()
17th Author's Name  
17th Author's Affiliation ()
18th Author's Name  
18th Author's Affiliation ()
19th Author's Name  
19th Author's Affiliation ()
20th Author's Name  
20th Author's Affiliation ()
Date Time 2010-01-29 13:25:00 
Presentation Time 25 
Registration for ICD 
Paper # IEICE-ICD2009-111 
Volume (vol) IEICE-109 
Number (no) no.405 
Page pp.99-104 
#Pages IEICE-6 
Date of Issue IEICE-ICD-2010-01-21 

[Return to Top Page]

[Return to IEICE Web Page]

The Institute of Electronics, Information and Communication Engineers (IEICE), Japan