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Paper Abstract and Keywords
Presentation 2010-01-27 14:55
An Estimation Method of Delay Time Variation by Crosstalk in Logic Circuit Level
Masayuki Kobayashi, Wataru Sento, Masahiko Toyonaga, Michiaki Muraoka (Kochi Univ.) VLD2009-95 CPSY2009-77 RECONF2009-80
Abstract (in Japanese) (See Japanese page) 
(in English) In this paper, a method which detects crosstalk points and timing error points by using the logic simulation with the back annotation of the delay time equation of crosstalk is proposed. The conventional method analyzed crosstalk with the static timing analysis and the circuit simulator. However, this method calculates the delay time increase of crosstalk by the delay time equation and can detect crosstalk points by using the logic simulation with the back annotation of the delay time. Furthermore, this method is able to detect crosstalk points which generate timing errors.
Keyword (in Japanese) (See Japanese page) 
(in English) Crosstalk / Design Methodology / Logic Simulation / EDA / CAD / / /  
Reference Info. IEICE Tech. Rep., vol. 109, no. 393, VLD2009-95, pp. 161-166, Jan. 2010.
Paper # VLD2009-95 
Date of Issue 2010-01-19 (VLD, CPSY, RECONF) 
ISSN Print edition: ISSN 0913-5685  Online edition: ISSN 2432-6380
Copyright
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reproduction
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF VLD2009-95 CPSY2009-77 RECONF2009-80

Conference Information
Committee IPSJ-SLDM VLD CPSY RECONF  
Conference Date 2010-01-26 - 2010-01-27 
Place (in Japanese) (See Japanese page) 
Place (in English) Keio Univ (Hiyoshi Campus) 
Topics (in Japanese) (See Japanese page) 
Topics (in English) FPGA Applications, etc 
Paper Information
Registration To VLD 
Conference Code 2010-01-SLDM-VLD-CPSY-RECONF 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) An Estimation Method of Delay Time Variation by Crosstalk in Logic Circuit Level 
Sub Title (in English)  
Keyword(1) Crosstalk  
Keyword(2) Design Methodology  
Keyword(3) Logic Simulation  
Keyword(4) EDA  
Keyword(5) CAD  
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1st Author's Name Masayuki Kobayashi  
1st Author's Affiliation Kochi University (Kochi Univ.)
2nd Author's Name Wataru Sento  
2nd Author's Affiliation Kochi University (Kochi Univ.)
3rd Author's Name Masahiko Toyonaga  
3rd Author's Affiliation Kochi University (Kochi Univ.)
4th Author's Name Michiaki Muraoka  
4th Author's Affiliation Kochi University (Kochi Univ.)
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Speaker
Date Time 2010-01-27 14:55:00 
Presentation Time 25 
Registration for VLD 
Paper # IEICE-VLD2009-95,IEICE-CPSY2009-77,IEICE-RECONF2009-80 
Volume (vol) IEICE-109 
Number (no) no.393(VLD), no.394(CPSY), no.395(RECONF) 
Page pp.161-166 
#Pages IEICE-6 
Date of Issue IEICE-VLD-2010-01-19,IEICE-CPSY-2010-01-19,IEICE-RECONF-2010-01-19 


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