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Paper Abstract and Keywords
Presentation 2010-01-27 10:00
Granularity Optimization Method for AES Encryption Implementation on CUDA
Naoki Nishikawa, Keisuke Iwai, Takakazu Kurokawa (NDA) VLD2009-86 CPSY2009-68 RECONF2009-71
Abstract (in Japanese) (See Japanese page) 
(in English) GPGPU as parallel computation platform has been noticed from almost all reseach fields. In particular CUDA occupies a high share of the GPGPU development environment. With CUDA,programmers are responsible for deciding the number of threads or thread blocks,but the optimum value is actually obtained by programmers’repetitive experiment. As the result,we have attempted to construct an automatic optimization model based on the number of threads used. As a first step,this paper presents analysis of how combinations such as data type of plaintext,memory allocation style of plaintext,and granularity,affect GPU performance. These experimental results show that there is up to a 6.6-fold performance increase among implementation methods with such combinations,resulting in the following insights: (1)Securing the number of threads,before the implementation of memory access optimization,is necessary. (2)16Byte/Thread granularity leads to higher GPU performance than 4Byte/Thread and 1Byte/Thread granularity. (3)Different data types in plaintext,memory allocation styles of plaintext,and granularity affect GPU performance. In addition,we confirmed AES encryption method with 4Byte/Thread granularity for plaintexts,stored in shared memory as both unsigned integer and structure of array leads to the GPU’s maximum performance and this implementation method achieved as apploximately 47-fold speed up as normal AES implemetation on Core i7-920 2.66GHz CPU.
Keyword (in Japanese) (See Japanese page) 
(in English) GPGPU / CUDA / Cipher / AES / Performance predication / / /  
Reference Info. IEICE Tech. Rep., vol. 109, no. 394, CPSY2009-68, pp. 107-112, Jan. 2010.
Paper # CPSY2009-68 
Date of Issue 2010-01-19 (VLD, CPSY, RECONF) 
ISSN Print edition: ISSN 0913-5685  Online edition: ISSN 2432-6380
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reproduction
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF VLD2009-86 CPSY2009-68 RECONF2009-71

Conference Information
Committee IPSJ-SLDM VLD CPSY RECONF  
Conference Date 2010-01-26 - 2010-01-27 
Place (in Japanese) (See Japanese page) 
Place (in English) Keio Univ (Hiyoshi Campus) 
Topics (in Japanese) (See Japanese page) 
Topics (in English) FPGA Applications, etc 
Paper Information
Registration To CPSY 
Conference Code 2010-01-SLDM-VLD-CPSY-RECONF 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) Granularity Optimization Method for AES Encryption Implementation on CUDA 
Sub Title (in English)  
Keyword(1) GPGPU  
Keyword(2) CUDA  
Keyword(3) Cipher  
Keyword(4) AES  
Keyword(5) Performance predication  
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1st Author's Name Naoki Nishikawa  
1st Author's Affiliation National Defense Academy (NDA)
2nd Author's Name Keisuke Iwai  
2nd Author's Affiliation National Defense Academy (NDA)
3rd Author's Name Takakazu Kurokawa  
3rd Author's Affiliation National Defense Academy (NDA)
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Speaker
Date Time 2010-01-27 10:00:00 
Presentation Time 25 
Registration for CPSY 
Paper # IEICE-VLD2009-86,IEICE-CPSY2009-68,IEICE-RECONF2009-71 
Volume (vol) IEICE-109 
Number (no) no.393(VLD), no.394(CPSY), no.395(RECONF) 
Page pp.107-112 
#Pages IEICE-6 
Date of Issue IEICE-VLD-2010-01-19,IEICE-CPSY-2010-01-19,IEICE-RECONF-2010-01-19 


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