Paper Abstract and Keywords |
Presentation |
2010-01-27 10:25
Effective Hardware Task Context Switching in Virtex-4 FPGAs Krzysztof Jozwik, Hiroyuki Tomiyama, Shinya Honda, Hiroaki Takada (Nagoya Univ.) VLD2009-87 CPSY2009-69 RECONF2009-72 |
Abstract |
(in Japanese) |
(See Japanese page) |
(in English) |
A unique aspect of flexibility provided by some of the FPGAs such as Xilinx Virtex-4 family is the capability of dynamic and partial reconfiguration, giving them additional leverage over the other co-existing FPGA solutions by allowing implementation of such concepts as a hardware task. When compared to classical software task effective employment of the new idea in preemptive multitasking systems poses many difficulties and involves many mechanisms such as context saving and restoring, to be built practically from the scratch. This paper presents an effective approach to high-speed context switching for Virtex4-based DPR (Dynamic Partial Reconfiguration) Systems based on developed embedded system infrastructure with lightweight control bus, enhancing management of reconfigurable hardware modules and very efficient, instruction-driven reconfiguration/readback controller which offers 78-fold speed-ups and further superior functionalities when compared to baseline IP provided by FPGA’s manufacturer. The whole system is additionally supported by developed bitstream manipulation tool intended for PC (Personal Computer) and used as a back-end program for current DPR design flow. |
Keyword |
(in Japanese) |
(See Japanese page) |
(in English) |
FPGA / Dynamic Partial Reconfiguration / HW Context-switch / / / / / |
Reference Info. |
IEICE Tech. Rep., vol. 109, no. 395, RECONF2009-72, pp. 113-118, Jan. 2010. |
Paper # |
RECONF2009-72 |
Date of Issue |
2010-01-19 (VLD, CPSY, RECONF) |
ISSN |
Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 |
Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) |
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VLD2009-87 CPSY2009-69 RECONF2009-72 |
Conference Information |
Committee |
IPSJ-SLDM VLD CPSY RECONF |
Conference Date |
2010-01-26 - 2010-01-27 |
Place (in Japanese) |
(See Japanese page) |
Place (in English) |
Keio Univ (Hiyoshi Campus) |
Topics (in Japanese) |
(See Japanese page) |
Topics (in English) |
FPGA Applications, etc |
Paper Information |
Registration To |
RECONF |
Conference Code |
2010-01-SLDM-VLD-CPSY-RECONF |
Language |
English |
Title (in Japanese) |
(See Japanese page) |
Sub Title (in Japanese) |
(See Japanese page) |
Title (in English) |
Effective Hardware Task Context Switching in Virtex-4 FPGAs |
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FPGA |
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Dynamic Partial Reconfiguration |
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HW Context-switch |
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1st Author's Name |
Krzysztof Jozwik |
1st Author's Affiliation |
Nagoya University (Nagoya Univ.) |
2nd Author's Name |
Hiroyuki Tomiyama |
2nd Author's Affiliation |
Nagoya University (Nagoya Univ.) |
3rd Author's Name |
Shinya Honda |
3rd Author's Affiliation |
Nagoya University (Nagoya Univ.) |
4th Author's Name |
Hiroaki Takada |
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Nagoya University (Nagoya Univ.) |
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Speaker |
Author-1 |
Date Time |
2010-01-27 10:25:00 |
Presentation Time |
25 minutes |
Registration for |
RECONF |
Paper # |
VLD2009-87, CPSY2009-69, RECONF2009-72 |
Volume (vol) |
vol.109 |
Number (no) |
no.393(VLD), no.394(CPSY), no.395(RECONF) |
Page |
pp.113-118 |
#Pages |
6 |
Date of Issue |
2010-01-19 (VLD, CPSY, RECONF) |
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