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| Presentation | 2010-01-27 10:50 Hardware Acceleration in a Scalable FPGA System Hironori Nakajo, Ryuichi Sakamoto (Tokyo Univ. of Agr and Tech.)  VLD2009-88 CPSY2009-70 RECONF2009-73 |
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| Abstract | (in Japanese) | (See Japanese page) |
| (in English) | Currently, FPGAs are utilized for hardware experiments or practices in many educational institutes. In a field of high performance computing, hardware acceleration with some FPGAs has been investigated in research institutes or HPC vendors. In this paper, experiments examples using FPGAs in some universities are introduced and researches of high performance computing systems with FPGAs are shown as well. Moreover, we propose a Scalable FPGA system which consists of several FPGA boards and multi-core processors each connected via fast serial link network. |
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| Keyword | (in Japanese) | (See Japanese page) |
| (in English) | FPGA / fast serial communication / high performance computing / / / / / | |
| Reference Info. | IEICE Tech. Rep., vol. 109, no. 395, RECONF2009-73, pp. 119-124, Jan. 2010. | |
| Paper # | RECONF2009-73 | |
| Date of Issue | 2010-01-19 (VLD, CPSY, RECONF) | |
| ISSN | Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 | |
| Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) | |
| Download PDF | VLD2009-88 CPSY2009-70 RECONF2009-73 |
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| Conference Information | |
| Committee | IPSJ-SLDM VLD CPSY RECONF |
| Conference Date | 2010-01-26 - 2010-01-27 |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | Keio Univ (Hiyoshi Campus) |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | FPGA Applications, etc |
| Paper Information | |
| Registration To | RECONF |
| Conference Code | 2010-01-SLDM-VLD-CPSY-RECONF |
| Language | Japanese |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Hardware Acceleration in a Scalable FPGA System |
| Sub Title (in English) | |
| Keyword(1) | FPGA |
| Keyword(2) | fast serial communication |
| Keyword(3) | high performance computing |
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| 1st Author's Name | Hironori Nakajo |
| 1st Author's Affiliation | Tokyo University of Agriculture and Technology (Tokyo Univ. of Agr and Tech.) |
| 2nd Author's Name | Ryuichi Sakamoto |
| 2nd Author's Affiliation | Tokyo University of Agriculture and Technology (Tokyo Univ. of Agr and Tech.) |
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| Speaker | Author-1 |
| Date Time | 2010-01-27 10:50:00 |
| Presentation Time | 25 minutes |
| Registration for | RECONF |
| Paper # | VLD2009-88, CPSY2009-70, RECONF2009-73 |
| Volume (vol) | vol.109 |
| Number (no) | no.393(VLD), no.394(CPSY), no.395(RECONF) |
| Page | pp.119-124 |
| #Pages | 6 |
| Date of Issue | 2010-01-19 (VLD, CPSY, RECONF) |
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