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Paper Abstract and Keywords
Presentation 2010-01-27 14:30
Fault Recovery Technique for Softcore Processor using Partial Reconfiguration
Yoshihiro Ichinomiya, Shiro Tanoue, Motoki Amagasaki, Morihiro Kuga, Toshinori Sueyoshi (Kumamoto Univ.) VLD2009-94 CPSY2009-76 RECONF2009-79
Abstract (in Japanese) (See Japanese page) 
(in English) This paper presents a technique for ensuring reliable softcore processor implemented on SRAM-based Field Programmable Gate Arrays (FPGAs). Although FPGA is easy to be attacked by Single Event Upsets (SEUs), it can clear these errors due to its reconfigurability. The circuit failure induced by SEU is able to mitigate and recover using Triple Modular Redundancy and Partial Reconfiguration. However, the reliability of the sequential circuit, such as processor, is not ensured only by these techniques, because the reconfiguration resets the states.We propose the synchronization technique after partial reconfiguration using a interrupt process. Additionally, we implement the Error Correcting Code to local memory to keep its reliability. Proposed system accomplish synchronization process only 6 $\mu s$ time overhead.
Keyword (in Japanese) (See Japanese page) 
(in English) TMR / Partial Reconfiguration / synchronization process / SEU / reliability / ECC / /  
Reference Info. IEICE Tech. Rep., vol. 109, no. 395, RECONF2009-79, pp. 155-160, Jan. 2010.
Paper # RECONF2009-79 
Date of Issue 2010-01-19 (VLD, CPSY, RECONF) 
ISSN Print edition: ISSN 0913-5685  Online edition: ISSN 2432-6380
Copyright
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reproduction
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF VLD2009-94 CPSY2009-76 RECONF2009-79

Conference Information
Committee IPSJ-SLDM VLD CPSY RECONF  
Conference Date 2010-01-26 - 2010-01-27 
Place (in Japanese) (See Japanese page) 
Place (in English) Keio Univ (Hiyoshi Campus) 
Topics (in Japanese) (See Japanese page) 
Topics (in English) FPGA Applications, etc 
Paper Information
Registration To RECONF 
Conference Code 2010-01-SLDM-VLD-CPSY-RECONF 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) Fault Recovery Technique for Softcore Processor using Partial Reconfiguration 
Sub Title (in English)  
Keyword(1) TMR  
Keyword(2) Partial Reconfiguration  
Keyword(3) synchronization process  
Keyword(4) SEU  
Keyword(5) reliability  
Keyword(6) ECC  
Keyword(7)  
Keyword(8)  
1st Author's Name Yoshihiro Ichinomiya  
1st Author's Affiliation Kumamoto University (Kumamoto Univ.)
2nd Author's Name Shiro Tanoue  
2nd Author's Affiliation Kumamoto University (Kumamoto Univ.)
3rd Author's Name Motoki Amagasaki  
3rd Author's Affiliation Kumamoto University (Kumamoto Univ.)
4th Author's Name Morihiro Kuga  
4th Author's Affiliation Kumamoto University (Kumamoto Univ.)
5th Author's Name Toshinori Sueyoshi  
5th Author's Affiliation Kumamoto University (Kumamoto Univ.)
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Speaker
Date Time 2010-01-27 14:30:00 
Presentation Time 25 
Registration for RECONF 
Paper # IEICE-VLD2009-94,IEICE-CPSY2009-76,IEICE-RECONF2009-79 
Volume (vol) IEICE-109 
Number (no) no.393(VLD), no.394(CPSY), no.395(RECONF) 
Page pp.155-160 
#Pages IEICE-6 
Date of Issue IEICE-VLD-2010-01-19,IEICE-CPSY-2010-01-19,IEICE-RECONF-2010-01-19 


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