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Paper Abstract and Keywords
Presentation 2010-01-26 16:45
Hardware Specialization of Digital Filters for Vibration Control
Yasuaki Tezuka, Shuichi Ichikawa, Yoshiyuki Noda (Toyohashi Univ. of Tech.) VLD2009-82 CPSY2009-64 RECONF2009-67
Abstract (in Japanese) (See Japanese page) 
(in English) The logic circuit can generally be reduced, if any input of the circuit is given as a constant. The derived circuit
might be even faster than the original, because of the reduction of logic depth and layout area. Since the derived circuit is
specialized to a specific input, such technique is called as hardware specialization. The purpose of this study is to evaluate
the hardware specialization technique in digital filters and vibration control systems. Altera Cyclone III FPGA and Quartus II
software were adopted as evaluation platform. In case of a third-order Butterworth low-pass filter, its logic scale was reduced
to 40–56% of the original by fixing the gain parameters. In a hybrid-shaped approach with a low-pass filter and a notch filter,
the logic scale was reduced to 48% of the original by fixing the parameters of these filters. In a preshaping circuit with a
low-pass filter, the respective logic scale was reduced to 7.5% and 11% of the original by fixing parameters and input wave
form. In the circuits specialized to a fixed wave form, the logic scale was a linear function of the bit width of the input data.
Keyword (in Japanese) (See Japanese page) 
(in English) FPGA / Digital Filter / Hardware Specialization / partial evaluation / / / /  
Reference Info. IEICE Tech. Rep., vol. 109, no. 395, RECONF2009-67, pp. 83-88, Jan. 2010.
Paper # RECONF2009-67 
Date of Issue 2010-01-19 (VLD, CPSY, RECONF) 
ISSN Print edition: ISSN 0913-5685  Online edition: ISSN 2432-6380
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技術研究報告に掲載された論文の著作権はIEICEに帰属します.(許諾番号:10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF VLD2009-82 CPSY2009-64 RECONF2009-67

Conference Information
Committee IPSJ-SLDM VLD CPSY RECONF  
Conference Date 2010-01-26 - 2010-01-27 
Place (in Japanese) (See Japanese page) 
Place (in English) Keio Univ (Hiyoshi Campus) 
Topics (in Japanese) (See Japanese page) 
Topics (in English) FPGA Applications, etc 
Paper Information
Registration To RECONF 
Conference Code 2010-01-SLDM-VLD-CPSY-RECONF 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) Hardware Specialization of Digital Filters for Vibration Control 
Sub Title (in English)  
Keyword(1) FPGA  
Keyword(2) Digital Filter  
Keyword(3) Hardware Specialization  
Keyword(4) partial evaluation  
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1st Author's Name Yasuaki Tezuka  
1st Author's Affiliation Toyohashi University of Technology (Toyohashi Univ. of Tech.)
2nd Author's Name Shuichi Ichikawa  
2nd Author's Affiliation Toyohashi University of Technology (Toyohashi Univ. of Tech.)
3rd Author's Name Yoshiyuki Noda  
3rd Author's Affiliation Toyohashi University of Technology (Toyohashi Univ. of Tech.)
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Speaker
Date Time 2010-01-26 16:45:00 
Presentation Time 25 
Registration for RECONF 
Paper # IEICE-VLD2009-82,IEICE-CPSY2009-64,IEICE-RECONF2009-67 
Volume (vol) IEICE-109 
Number (no) no.393(VLD), no.394(CPSY), no.395(RECONF) 
Page pp.83-88 
#Pages IEICE-6 
Date of Issue IEICE-VLD-2010-01-19,IEICE-CPSY-2010-01-19,IEICE-RECONF-2010-01-19 


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