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| Presentation | 2010-01-26 14:30 A Non-Minimal Fully Adaptive Routing Using a Single-Flit Packet Structure Yuri Nishikawa (Keio Univ.), Michihiro Koibuchi (NII), Hiroki Matsutani (Tokyo Univ.), Hideharu Amano (Keio Univ.)  VLD2009-78 CPSY2009-60 RECONF2009-63 |
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| Abstract | (in Japanese) | (See Japanese page) |
| (in English) | We propose a non-minimal fully adaptive routing methodology which does not require the use of virtual channels for its network-on-chip routers. To guarantee deadlock-free packet transfer, we adopted the following approaches: (1) a non-blocking packet transfer among certain routers, and (2) the use of a single-flit packet structure. As the result of throughput evaluation, the proposed methodology provided 2.48 times higher throughput compared to other typical non-minimal adaptive routing algorithms. |
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| Keyword | (in Japanese) | (See Japanese page) |
| (in English) | Network-on-Chip / routing algorithm / deadlock freedom / single-flit packet / interconnection network / / / | |
| Reference Info. | IEICE Tech. Rep., vol. 109, no. 394, CPSY2009-60, pp. 53-58, Jan. 2010. | |
| Paper # | CPSY2009-60 | |
| Date of Issue | 2010-01-19 (VLD, CPSY, RECONF) | |
| ISSN | Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 | |
| Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) | |
| Download PDF | VLD2009-78 CPSY2009-60 RECONF2009-63 |
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| Conference Information | |
| Committee | IPSJ-SLDM VLD CPSY RECONF |
| Conference Date | 2010-01-26 - 2010-01-27 |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | Keio Univ (Hiyoshi Campus) |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | FPGA Applications, etc |
| Paper Information | |
| Registration To | CPSY |
| Conference Code | 2010-01-SLDM-VLD-CPSY-RECONF |
| Language | Japanese |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | A Non-Minimal Fully Adaptive Routing Using a Single-Flit Packet Structure |
| Sub Title (in English) | |
| Keyword(1) | Network-on-Chip |
| Keyword(2) | routing algorithm |
| Keyword(3) | deadlock freedom |
| Keyword(4) | single-flit packet |
| Keyword(5) | interconnection network |
| Keyword(6) | |
| Keyword(7) | |
| Keyword(8) | |
| 1st Author's Name | Yuri Nishikawa |
| 1st Author's Affiliation | Keio University (Keio Univ.) |
| 2nd Author's Name | Michihiro Koibuchi |
| 2nd Author's Affiliation | National Institute of Informatics (NII) |
| 3rd Author's Name | Hiroki Matsutani |
| 3rd Author's Affiliation | Tokyo University (Tokyo Univ.) |
| 4th Author's Name | Hideharu Amano |
| 4th Author's Affiliation | Keio University (Keio Univ.) |
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| Speaker | Author-1 |
| Date Time | 2010-01-26 14:30:00 |
| Presentation Time | 25 minutes |
| Registration for | CPSY |
| Paper # | VLD2009-78, CPSY2009-60, RECONF2009-63 |
| Volume (vol) | vol.109 |
| Number (no) | no.393(VLD), no.394(CPSY), no.395(RECONF) |
| Page | pp.53-58 |
| #Pages | 6 |
| Date of Issue | 2010-01-19 (VLD, CPSY, RECONF) |
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