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Paper Abstract and Keywords
Presentation 2010-01-26 14:55
Design of Reconfigurable Logic Device based on Variable Grain Logic Cell
Kazuki Inoue, Yasuhiro Okamoto, Qian Zhao, Komei Yoshizawa, Hiroki Yosho, Masahiro Koga, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi (Kumamoto Univ.) VLD2009-79 CPSY2009-61 RECONF2009-64
Abstract (in Japanese) (See Japanese page) 
(in English) We propose a variable grain logic cell(VGLC)architecture. Its key feature is variable granularity which helps to create a balance between two types of devices: coarse-grain type and fine-grain type.Because of
this, the VGLC can achived high-performance on any applications. In this paper, we describe the VGLC prototype chip designed in e-Shuttle 65nm library. In addition, in order to implement circuits, we newly developed the configuration bit stream generator. At last, we verified the function of the designed chip and bit stream generator by
implementing the 4-bit counter circuit.
Keyword (in Japanese) (See Japanese page) 
(in English) Coarse-grain type / Fine-grain type / prototyping / / / / /  
Reference Info. IEICE Tech. Rep., vol. 109, no. 395, RECONF2009-64, pp. 59-64, Jan. 2010.
Paper # RECONF2009-64 
Date of Issue 2010-01-19 (VLD, CPSY, RECONF) 
ISSN Print edition: ISSN 0913-5685  Online edition: ISSN 2432-6380
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF VLD2009-79 CPSY2009-61 RECONF2009-64

Conference Information
Conference Date 2010-01-26 - 2010-01-27 
Place (in Japanese) (See Japanese page) 
Place (in English) Keio Univ (Hiyoshi Campus) 
Topics (in Japanese) (See Japanese page) 
Topics (in English) FPGA Applications, etc 
Paper Information
Registration To RECONF 
Conference Code 2010-01-SLDM-VLD-CPSY-RECONF 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) Design of Reconfigurable Logic Device based on Variable Grain Logic Cell 
Sub Title (in English)  
Keyword(1) Coarse-grain type  
Keyword(2) Fine-grain type  
Keyword(3) prototyping  
1st Author's Name Kazuki Inoue  
1st Author's Affiliation Kumamoto University (Kumamoto Univ.)
2nd Author's Name Yasuhiro Okamoto  
2nd Author's Affiliation Kumamoto University (Kumamoto Univ.)
3rd Author's Name Qian Zhao  
3rd Author's Affiliation Kumamoto University (Kumamoto Univ.)
4th Author's Name Komei Yoshizawa  
4th Author's Affiliation Kumamoto University (Kumamoto Univ.)
5th Author's Name Hiroki Yosho  
5th Author's Affiliation Kumamoto University (Kumamoto Univ.)
6th Author's Name Masahiro Koga  
6th Author's Affiliation Kumamoto University (Kumamoto Univ.)
7th Author's Name Motoki Amagasaki  
7th Author's Affiliation Kumamoto University (Kumamoto Univ.)
8th Author's Name Masahiro Iida  
8th Author's Affiliation Kumamoto University (Kumamoto Univ.)
9th Author's Name Morihiro Kuga  
9th Author's Affiliation Kumamoto University (Kumamoto Univ.)
10th Author's Name Toshinori Sueyoshi  
10th Author's Affiliation Kumamoto University (Kumamoto Univ.)
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Date Time 2010-01-26 14:55:00 
Presentation Time 25 
Registration for RECONF 
Paper # IEICE-VLD2009-79,IEICE-CPSY2009-61,IEICE-RECONF2009-64 
Volume (vol) IEICE-109 
Number (no) no.393(VLD), no.394(CPSY), no.395(RECONF) 
Page pp.59-64 
#Pages IEICE-6 
Date of Issue IEICE-VLD-2010-01-19,IEICE-CPSY-2010-01-19,IEICE-RECONF-2010-01-19 

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