Paper Abstract and Keywords |
Presentation |
2009-12-15 17:00
A 3D Processor Using Inductive-Coupling Inter-Chip Link
-- 3D System Integration of a 90nm CMOS Processor and a 65nm CMOS SRAM -- Kiichi Niitsu (Keio Univ./JST), Yasuhisa Shimazaki (Keio Univ./Renesas Technology), Yasufumi Sugimori, Yoshinori Kohama, Kazutaka Kasuga (Keio Univ.), Itaru Nonomura (Renesas Technology), Makoto Saen, Shigenobu Komatsu, Kenichi Osada, Naohiko Irie (Hitachi), Toshihiro Hattori, Atsushi Hasegawa (Renesas Technology), Tadahiro Kuroda (Keio Univ.) ICD2009-105 Link to ES Tech. Rep. Archives: ICD2009-105 |
Abstract |
(in Japanese) |
(See Japanese page) |
(in English) |
A 90nm CMOS processor is mounted face down on a package by C4 bump and a 65nm CMOS 1MB SRAM is glued on it face up. The two chips under different supply voltages are AC-coupled by inductive coupling that provides 19.2Gb/s data link. Measured power and area efficiency of the link is 1pJ/b and 0.15mm^2/Gbps, which is 1/30 and 1/3 in comparison with the DDR2 interface respectively. Furthermore, multi-SRAM stacking incorporating a wire-penetrating technique and an open-skipped inductor scheme is successfully demonstrated. |
Keyword |
(in Japanese) |
(See Japanese page) |
(in English) |
CMOS / Processor / Memory / Inductive-Coupling / Wireless Communication / Inter-Chip Interface / Low-Power Technique / 3D Integration |
Reference Info. |
IEICE Tech. Rep., vol. 109, no. 336, ICD2009-105, pp. 163-168, Dec. 2009. |
Paper # |
ICD2009-105 |
Date of Issue |
2009-12-07 (ICD) |
ISSN |
Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 |
Copyright and reproduction |
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ICD2009-105 Link to ES Tech. Rep. Archives: ICD2009-105 |
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