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| Presentation | 2009-12-03 10:40 An Approach to Dependable Chip Multiprocessors with Process Pair and Swap Mechanism Tomohide Nagai, Masashi Imai, Takashi Nanya (Univ. of Tokyo)  VLD2009-51 DC2009-38 |
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| Abstract | (in Japanese) | (See Japanese page) |
| (in English) | With the down scale of technology and the increase of transistor count, future processors are expected to be more susceptible to faults. In this paper, we propose a processor-level fault tolerance technique for chip Multi-processors called ``Pair & Swap'' (P\&S). We also propose a new metric called ``Mean Computation To Failure'' (MCTF) considering not only reliability but also performance. We evaluate the P\&S and the traditional triple modular redundancy (TMR) by MCTF.The result shows that the MCTF of the P\&S is about 1.5 times larger than that of the dynamic TMR. |
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| Keyword | (in Japanese) | (See Japanese page) |
| (in English) | Pair & Swap / graceful degradation / dependable chip multiprocessor / mean computation to failure / / / / | |
| Reference Info. | IEICE Tech. Rep., vol. 109, no. 316, DC2009-38, pp. 67-72, Dec. 2009. | |
| Paper # | DC2009-38 | |
| Date of Issue | 2009-11-25 (VLD, DC) | |
| ISSN | Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 | |
| Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) | |
| Download PDF | VLD2009-51 DC2009-38 |
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| Conference Information | |
| Committee | VLD DC IPSJ-SLDM CPSY RECONF ICD CPM |
| Conference Date | 2009-12-02 - 2009-12-04 |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | Kochi City Culture-Plaza |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | Design Gaia 2009 ―New Field of VLSI Design― |
| Paper Information | |
| Registration To | DC |
| Conference Code | 2009-12-VLD-DC-SLDM-CPSY-RECONF-ICD-CPM |
| Language | Japanese |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | An Approach to Dependable Chip Multiprocessors with Process Pair and Swap Mechanism |
| Sub Title (in English) | |
| Keyword(1) | Pair & Swap |
| Keyword(2) | graceful degradation |
| Keyword(3) | dependable chip multiprocessor |
| Keyword(4) | mean computation to failure |
| Keyword(5) | |
| Keyword(6) | |
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| 1st Author's Name | Tomohide Nagai |
| 1st Author's Affiliation | University of Tokyo (Univ. of Tokyo) |
| 2nd Author's Name | Masashi Imai |
| 2nd Author's Affiliation | University of Tokyo (Univ. of Tokyo) |
| 3rd Author's Name | Takashi Nanya |
| 3rd Author's Affiliation | University of Tokyo (Univ. of Tokyo) |
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| Speaker | Author-1 |
| Date Time | 2009-12-03 10:40:00 |
| Presentation Time | 20 minutes |
| Registration for | DC |
| Paper # | VLD2009-51, DC2009-38 |
| Volume (vol) | vol.109 |
| Number (no) | no.315(VLD), no.316(DC) |
| Page | pp.67-72 |
| #Pages | 6 |
| Date of Issue | 2009-11-25 (VLD, DC) |
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