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| Presentation | 2009-12-02 10:40 Implementation of Asynchronous Bus for GALS System Takehiro Hori, Tsugio Nakamura, Narito Fuyutsume, Hiroshi Kasahara, Teruo Tanaka (Tokyo Denki Univ.)  CPM2009-135 ICD2009-64 Link to ES Tech. Rep. Archives: CPM2009-135 ICD2009-64 |
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| Abstract | (in Japanese) | (See Japanese page) |
| (in English) | Although asynchronous circuit can solve problems of power consumption, speed, noise, and clockskew, the transmission is possible only for 1 to 1 communication and uni-directional. The paper suggests a bus method in the asynchronous circuit with the imitated broadcast function used in the synchronous circuit. It is also designed to be able to cope with the GALS network where synchronous and asynchronous circuits are coexisted. As a result, low-power, high-speed, low noise and stable “network on chip(NoC)” is accomplished where the existing design resources are reusable. We report the circuit implemented on FPGA and its confirmed stable operation. | |
| Keyword | (in Japanese) | (See Japanese page) |
| (in English) | NoC / GALS / Asynchronous Circuit / Bus Architecture / On Chip Bus / / / | |
| Reference Info. | IEICE Tech. Rep., vol. 109, no. 318, ICD2009-64, pp. 7-12, Dec. 2009. | |
| Paper # | ICD2009-64 | |
| Date of Issue | 2009-11-25 (CPM, ICD) | |
| ISSN | Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 | |
| Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) | |
| Download PDF | CPM2009-135 ICD2009-64 Link to ES Tech. Rep. Archives: CPM2009-135 ICD2009-64 |
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| Conference Information | |
| Committee | VLD DC IPSJ-SLDM CPSY RECONF ICD CPM |
| Conference Date | 2009-12-02 - 2009-12-04 |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | Kochi City Culture-Plaza |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | Design Gaia 2009 ―New Field of VLSI Design― |
| Paper Information | |
| Registration To | ICD |
| Conference Code | 2009-12-VLD-DC-SLDM-CPSY-RECONF-ICD-CPM |
| Language | Japanese |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Implementation of Asynchronous Bus for GALS System |
| Sub Title (in English) | |
| Keyword(1) | NoC |
| Keyword(2) | GALS |
| Keyword(3) | Asynchronous Circuit |
| Keyword(4) | Bus Architecture |
| Keyword(5) | On Chip Bus |
| Keyword(6) | |
| Keyword(7) | |
| Keyword(8) | |
| 1st Author's Name | Takehiro Hori |
| 1st Author's Affiliation | Tokyo Denki University (Tokyo Denki Univ.) |
| 2nd Author's Name | Tsugio Nakamura |
| 2nd Author's Affiliation | Tokyo Denki University (Tokyo Denki Univ.) |
| 3rd Author's Name | Narito Fuyutsume |
| 3rd Author's Affiliation | Tokyo Denki University (Tokyo Denki Univ.) |
| 4th Author's Name | Hiroshi Kasahara |
| 4th Author's Affiliation | Tokyo Denki University (Tokyo Denki Univ.) |
| 5th Author's Name | Teruo Tanaka |
| 5th Author's Affiliation | Tokyo Denki University (Tokyo Denki Univ.) |
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| Speaker | Author-1 |
| Date Time | 2009-12-02 10:40:00 |
| Presentation Time | 20 minutes |
| Registration for | ICD |
| Paper # | CPM2009-135, ICD2009-64 |
| Volume (vol) | vol.109 |
| Number (no) | no.317(CPM), no.318(ICD) |
| Page | pp.7-12 |
| #Pages | 6 |
| Date of Issue | 2009-11-25 (CPM, ICD) |
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