Paper Abstract and Keywords |
Presentation |
2009-12-02 16:00
Simulation-Based Bus Width Optimization for Two-Level Cache Shinta Watanabe, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki (Waseda Univ.) VLD2009-48 DC2009-35 |
Abstract |
(in Japanese) |
(See Japanese page) |
(in English) |
In this paper, we propose a simulation-based bus width and cache configuration optimization approach for two-level caches. First, we show that we can consider the cache hit/miss judgement and the bus width optimization independently. Second,the cache hit/mis judgments can be done effectively by applying our CRCB techniques. Then we show several properties for cache and bus width and propose an effective bus width optimization approach based on them. We have developed a system that optimizes cache and bus configuration where total memory access time or total energy consumption is minimized. Our proposed approach totally runs a maximum of 835.91 faster compared to the simple exhaustive approach. |
Keyword |
(in Japanese) |
(See Japanese page) |
(in English) |
cache memory / bus width / cache simulation / cache optimization / bus width optimization / / / |
Reference Info. |
IEICE Tech. Rep., vol. 109, no. 315, VLD2009-48, pp. 43-48, Dec. 2009. |
Paper # |
VLD2009-48 |
Date of Issue |
2009-11-25 (VLD, DC) |
ISSN |
Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 |
Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) |
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VLD2009-48 DC2009-35 |
Conference Information |
Committee |
VLD DC IPSJ-SLDM CPSY RECONF ICD CPM |
Conference Date |
2009-12-02 - 2009-12-04 |
Place (in Japanese) |
(See Japanese page) |
Place (in English) |
Kochi City Culture-Plaza |
Topics (in Japanese) |
(See Japanese page) |
Topics (in English) |
Design Gaia 2009 ―New Field of VLSI Design― |
Paper Information |
Registration To |
VLD |
Conference Code |
2009-12-VLD-DC-SLDM-CPSY-RECONF-ICD-CPM |
Language |
Japanese |
Title (in Japanese) |
(See Japanese page) |
Sub Title (in Japanese) |
(See Japanese page) |
Title (in English) |
Simulation-Based Bus Width Optimization for Two-Level Cache |
Sub Title (in English) |
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Keyword(1) |
cache memory |
Keyword(2) |
bus width |
Keyword(3) |
cache simulation |
Keyword(4) |
cache optimization |
Keyword(5) |
bus width optimization |
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1st Author's Name |
Shinta Watanabe |
1st Author's Affiliation |
Waseda University (Waseda Univ.) |
2nd Author's Name |
Nozomu Togawa |
2nd Author's Affiliation |
Waseda University (Waseda Univ.) |
3rd Author's Name |
Masao Yanagisawa |
3rd Author's Affiliation |
Waseda University (Waseda Univ.) |
4th Author's Name |
Tatsuo Ohtsuki |
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Waseda University (Waseda Univ.) |
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Speaker |
Author-1 |
Date Time |
2009-12-02 16:00:00 |
Presentation Time |
20 minutes |
Registration for |
VLD |
Paper # |
VLD2009-48, DC2009-35 |
Volume (vol) |
vol.109 |
Number (no) |
no.315(VLD), no.316(DC) |
Page |
pp.43-48 |
#Pages |
6 |
Date of Issue |
2009-11-25 (VLD, DC) |
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