Paper Abstract and Keywords |
Presentation |
2009-10-02 17:50
Delay Variation Tolerant Subthreshold Digital Circuits for Ultra-Low Power Yuji Osaki, Tetsuya Hirose, Kei Matsumoto, Nobutaka Kuroki, Masahiro Numa (Kobe Univ.) ICD2009-62 Link to ES Tech. Rep. Archives: ICD2009-62 |
Abstract |
(in Japanese) |
(See Japanese page) |
(in English) |
Subthreshold LSIs can achieve ultra-low power. However, threshold voltage variations with temperature and fabrication process have significant impact on the circuit performance. In subthreshold digital circuits, delay time changes exponentially with threshold-voltage variations. To solve this problem, we propose a delay-compensation technique for subthreshold digital circuits. On-chip threshold-voltage monitoring and supply-voltage scaling are adopted to mitigate threshold-voltage variations. As examples of subthreshold digital circuits, we have evaluated the delay time in a ring oscillator and an 8-bit ripple carry adder. With the proposed techinque, the delay time can be improved from log-normal to normal distribution. |
Keyword |
(in Japanese) |
(See Japanese page) |
(in English) |
Subthreshold operation / Digital circuits / Variation / Delay compensation / / / / |
Reference Info. |
IEICE Tech. Rep., vol. 109, no. 214, ICD2009-62, pp. 165-170, Oct. 2009. |
Paper # |
ICD2009-62 |
Date of Issue |
2009-09-24 (ICD) |
ISSN |
Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 |
Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) |
Download PDF |
ICD2009-62 Link to ES Tech. Rep. Archives: ICD2009-62 |
Conference Information |
Committee |
ICD ITE-IST |
Conference Date |
2009-10-01 - 2009-10-02 |
Place (in Japanese) |
(See Japanese page) |
Place (in English) |
CIC Tokyo (Tamachi) |
Topics (in Japanese) |
(See Japanese page) |
Topics (in English) |
Analog, Mixed analog and digital, RF, and sensor interface circuitry |
Paper Information |
Registration To |
ICD |
Conference Code |
2009-10-ICD-IST |
Language |
Japanese |
Title (in Japanese) |
(See Japanese page) |
Sub Title (in Japanese) |
(See Japanese page) |
Title (in English) |
Delay Variation Tolerant Subthreshold Digital Circuits for Ultra-Low Power |
Sub Title (in English) |
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Keyword(1) |
Subthreshold operation |
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Digital circuits |
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Variation |
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Delay compensation |
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1st Author's Name |
Yuji Osaki |
1st Author's Affiliation |
Kobe University (Kobe Univ.) |
2nd Author's Name |
Tetsuya Hirose |
2nd Author's Affiliation |
Kobe University (Kobe Univ.) |
3rd Author's Name |
Kei Matsumoto |
3rd Author's Affiliation |
Kobe University (Kobe Univ.) |
4th Author's Name |
Nobutaka Kuroki |
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Kobe University (Kobe Univ.) |
5th Author's Name |
Masahiro Numa |
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Kobe University (Kobe Univ.) |
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Speaker |
Author-1 |
Date Time |
2009-10-02 17:50:00 |
Presentation Time |
25 minutes |
Registration for |
ICD |
Paper # |
ICD2009-62 |
Volume (vol) |
vol.109 |
Number (no) |
no.214 |
Page |
pp.165-170 |
#Pages |
6 |
Date of Issue |
2009-09-24 (ICD) |
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