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| Presentation | 2009-10-01 09:35 A 6-bit Arbitrary Digital Noise Emulator in 65nm CMOS Technology Daisuke Fujimoto, Tetsuro Matsuno (Kobe Univ.), Daisuke Kosaka (A-R-Tec), Naoyuki Hamanishi, Ken Tanabe, Masazumi Shiochi (Toshiba Corp.), Makoto Nagata (Kobe Univ./A-R-Tec)  ICD2009-34 Link to ES Tech. Rep. Archives: ICD2009-34 |
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| Abstract | (in Japanese) | (See Japanese page) |
| (in English) | An arbitrary noise generator (ANG) is based on time-series charging of divided parasitic capacitance (TSDPC) and emulates power supply noise generation in a CMOS digital circuit. A prototype ANG incorporates an array of 32 × 32 6-bit TSDPC cells along with a 128-word vector memory and occupies 2 × 2 mm2 in a 65 nm 1.2 V CMOS technology. Digital noise emulation of functional logic cores such as register arrays and processing elements is demonstrated with chip-level waveform monitoring at power supply, ground, as well as substrate nodes. |
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| Keyword | (in Japanese) | (See Japanese page) |
| (in English) | TSDPC model / Power supply noise / / / / / / | |
| Reference Info. | IEICE Tech. Rep., vol. 109, no. 214, ICD2009-34, pp. 7-10, Oct. 2009. | |
| Paper # | ICD2009-34 | |
| Date of Issue | 2009-09-24 (ICD) | |
| ISSN | Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 | |
| Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) | |
| Download PDF | ICD2009-34 Link to ES Tech. Rep. Archives: ICD2009-34 |
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| Conference Information | |
| Committee | ICD ITE-IST |
| Conference Date | 2009-10-01 - 2009-10-02 |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | CIC Tokyo (Tamachi) |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | Analog, Mixed analog and digital, RF, and sensor interface circuitry |
| Paper Information | |
| Registration To | ICD |
| Conference Code | 2009-10-ICD-IST |
| Language | Japanese |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | A 6-bit Arbitrary Digital Noise Emulator in 65nm CMOS Technology |
| Sub Title (in English) | |
| Keyword(1) | TSDPC model |
| Keyword(2) | Power supply noise |
| Keyword(3) | |
| Keyword(4) | |
| Keyword(5) | |
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| Keyword(7) | |
| Keyword(8) | |
| 1st Author's Name | Daisuke Fujimoto |
| 1st Author's Affiliation | Kobe University (Kobe Univ.) |
| 2nd Author's Name | Tetsuro Matsuno |
| 2nd Author's Affiliation | Kobe University (Kobe Univ.) |
| 3rd Author's Name | Daisuke Kosaka |
| 3rd Author's Affiliation | A-R-Tec Corporation (A-R-Tec) |
| 4th Author's Name | Naoyuki Hamanishi |
| 4th Author's Affiliation | Toshiba Corporation (Toshiba Corp.) |
| 5th Author's Name | Ken Tanabe |
| 5th Author's Affiliation | Toshiba Corporation (Toshiba Corp.) |
| 6th Author's Name | Masazumi Shiochi |
| 6th Author's Affiliation | Toshiba Corporation (Toshiba Corp.) |
| 7th Author's Name | Makoto Nagata |
| 7th Author's Affiliation | Kobe University/A-R-Tec Corporation (Kobe Univ./A-R-Tec) |
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| Speaker | Author-1 |
| Date Time | 2009-10-01 09:35:00 |
| Presentation Time | 25 minutes |
| Registration for | ICD |
| Paper # | ICD2009-34 |
| Volume (vol) | vol.109 |
| Number (no) | no.214 |
| Page | pp.7-10 |
| #Pages | 4 |
| Date of Issue | 2009-09-24 (ICD) |
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