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| Presentation | 2009-09-18 10:50 An FPGA-based Tiny Processing System for Small Embedded System and Education Koji Nakano, Yasuaki Ito, Kensuke Kawakami, Koji Shigemoto (Hiroshima Univ)  RECONF2009-32 |
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| Abstract | (in Japanese) | (See Japanese page) |
| (in English) | The main contribution of this paper is to present a simple, scalable, and portable tiny processing system which can be implemented in various FPGAs. Our processing system includes a 16-bit processor, a cross assembler, and a cross compiler. Our tiny processing system has been used for the embedded system and a course material for graduate course education. As real-life applications, we have developed a PONG-like mini game and an RSA encryption/decryption systembased on the tiny processing system. Therefore, our tiny processing system benefits computer system education and small embedded system development. |
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| Keyword | (in Japanese) | (See Japanese page) |
| (in English) | Embedded System / CPU / Verilog HDL / Education / / / / | |
| Reference Info. | IEICE Tech. Rep., vol. 109, no. 198, RECONF2009-32, pp. 79-84, Sept. 2009. | |
| Paper # | RECONF2009-32 | |
| Date of Issue | 2009-09-10 (RECONF) | |
| ISSN | Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 | |
| Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) | |
| Download PDF | RECONF2009-32 |
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| Conference Information | |
| Committee | RECONF |
| Conference Date | 2009-09-17 - 2009-09-18 |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | Utsunomiya Univ. |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | Reconfigurable Sysytems, etc. |
| Paper Information | |
| Registration To | RECONF |
| Conference Code | 2009-09-RECONF |
| Language | English |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | An FPGA-based Tiny Processing System for Small Embedded System and Education |
| Sub Title (in English) | |
| Keyword(1) | Embedded System |
| Keyword(2) | CPU |
| Keyword(3) | Verilog HDL |
| Keyword(4) | Education |
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| 1st Author's Name | Koji Nakano |
| 1st Author's Affiliation | Hiroshima University (Hiroshima Univ) |
| 2nd Author's Name | Yasuaki Ito |
| 2nd Author's Affiliation | Hiroshima University (Hiroshima Univ) |
| 3rd Author's Name | Kensuke Kawakami |
| 3rd Author's Affiliation | Hiroshima University (Hiroshima Univ) |
| 4th Author's Name | Koji Shigemoto |
| 4th Author's Affiliation | Hiroshima University (Hiroshima Univ) |
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| Speaker | Author-1 |
| Date Time | 2009-09-18 10:50:00 |
| Presentation Time | 25 minutes |
| Registration for | RECONF |
| Paper # | RECONF2009-32 |
| Volume (vol) | vol.109 |
| Number (no) | no.198 |
| Page | pp.79-84 |
| #Pages | 6 |
| Date of Issue | 2009-09-10 (RECONF) |
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