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| Presentation | 2009-09-18 15:25 An FPGA-based Architecture for Verifying Collatz Conjecture Yasuaki Ito, Koji Nakano (Hiroshima Univ.)  RECONF2009-40 |
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| Abstract | (in Japanese) | (See Japanese page) |
| (in English) | Consider the following operation on an arbitrary positive number: if the number is even, divide it by two, and if the number is odd, triple it and add one. The Collatz conjecture assert that, starting from any positive number $n$, repeated iteration of the operations eventually produces the value $1$. The main contribution of this paper is to present hardware-software cooperative approach to verify the Collatz conjecture. The key idea of our approach is to sieve numbers $n$ that produces 1 using a circuit implemented on an FPGA. The numbers that fail to be verified by overflow are reported to the host PC. The host PC verifies those numbers using unlimited bits operations by software. We have implemented 24 coprocessors on the Vertex II family FPGA XC2V3000-4. The experimental results show that our hardware-software cooperative approach can verify $2.89 \times 10^9$ 64-bit numbers per second. | |
| Keyword | (in Japanese) | (See Japanese page) |
| (in English) | Hardware Algorithm / FPGA Implementation / Block RAMs / / / / / | |
| Reference Info. | IEICE Tech. Rep., vol. 109, no. 198, RECONF2009-40, pp. 125-130, Sept. 2009. | |
| Paper # | RECONF2009-40 | |
| Date of Issue | 2009-09-10 (RECONF) | |
| ISSN | Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 | |
| Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) | |
| Download PDF | RECONF2009-40 |
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| Conference Information | |
| Committee | RECONF |
| Conference Date | 2009-09-17 - 2009-09-18 |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | Utsunomiya Univ. |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | Reconfigurable Sysytems, etc. |
| Paper Information | |
| Registration To | RECONF |
| Conference Code | 2009-09-RECONF |
| Language | English |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | An FPGA-based Architecture for Verifying Collatz Conjecture |
| Sub Title (in English) | |
| Keyword(1) | Hardware Algorithm |
| Keyword(2) | FPGA Implementation |
| Keyword(3) | Block RAMs |
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| 1st Author's Name | Yasuaki Ito |
| 1st Author's Affiliation | Hiroshima University (Hiroshima Univ.) |
| 2nd Author's Name | Koji Nakano |
| 2nd Author's Affiliation | Hiroshima University (Hiroshima Univ.) |
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| Speaker | Author-1 |
| Date Time | 2009-09-18 15:25:00 |
| Presentation Time | 25 minutes |
| Registration for | RECONF |
| Paper # | RECONF2009-40 |
| Volume (vol) | vol.109 |
| Number (no) | no.198 |
| Page | pp.125-130 |
| #Pages | 6 |
| Date of Issue | 2009-09-10 (RECONF) |
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