Paper Abstract and Keywords |
Presentation |
2009-09-17 16:05
Leakage Power Reduction of a Dynamically Reconfigurable Processors with Deal Vth cells Hideharu Amano, Keiichiro Hirai, Toru Sano, Masaru Kato, Yoshiki Saito (Keio Univ.) RECONF2009-26 |
Abstract |
(in Japanese) |
(See Japanese page) |
(in English) |
One of benefit of coarse-grained dynamically
reconfigurable processor arrays (DRPAs)
is its low dynamic power consumption by operating
a number of processing element
(PE) in parallel with low frequency.
However, in the future advanced process,
the leakage power will occupy a considerable
part of the total power consumption, and it may degrade the advantage of DRPAs.
In order to reduce the leakage power of DRPA without severe performance
degradation, eight design policies ({\em Mult, Sw, MultSw, MapHalf, 1Low,
RandHalf, Sw+Half} and {\em SW+Mult})
with Dual-Vt cells are proposed and evaluated
based on a prototype DRPA called MuCCRA-3T.
Evaluation results show that {\em Sw} in which Low-Vt cells are only used
in switching elements of the array achieved the best power-delay product.
If performance of Sw is not enough, {\em Sw+Half} in which
Low-Vt cells are used in a lower half PEs and all switching elements
improve 24\% of the leakage power with 5\%-14\% of extra delay time of
the design with all Low-Vt cells. |
Keyword |
(in Japanese) |
(See Japanese page) |
(in English) |
Dynamically Reconfigurable Processor / Low Power Design / Dual-Vth / / / / / |
Reference Info. |
IEICE Tech. Rep., vol. 109, no. 198, RECONF2009-26, pp. 43-48, Sept. 2009. |
Paper # |
RECONF2009-26 |
Date of Issue |
2009-09-10 (RECONF) |
ISSN |
Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 |
Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) |
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RECONF2009-26 |
Conference Information |
Committee |
RECONF |
Conference Date |
2009-09-17 - 2009-09-18 |
Place (in Japanese) |
(See Japanese page) |
Place (in English) |
Utsunomiya Univ. |
Topics (in Japanese) |
(See Japanese page) |
Topics (in English) |
Reconfigurable Sysytems, etc. |
Paper Information |
Registration To |
RECONF |
Conference Code |
2009-09-RECONF |
Language |
Japanese |
Title (in Japanese) |
(See Japanese page) |
Sub Title (in Japanese) |
(See Japanese page) |
Title (in English) |
Leakage Power Reduction of a Dynamically Reconfigurable Processors with Deal Vth cells |
Sub Title (in English) |
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Keyword(1) |
Dynamically Reconfigurable Processor |
Keyword(2) |
Low Power Design |
Keyword(3) |
Dual-Vth |
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1st Author's Name |
Hideharu Amano |
1st Author's Affiliation |
Keio University (Keio Univ.) |
2nd Author's Name |
Keiichiro Hirai |
2nd Author's Affiliation |
Keio University (Keio Univ.) |
3rd Author's Name |
Toru Sano |
3rd Author's Affiliation |
Keio University (Keio Univ.) |
4th Author's Name |
Masaru Kato |
4th Author's Affiliation |
Keio University (Keio Univ.) |
5th Author's Name |
Yoshiki Saito |
5th Author's Affiliation |
Keio University (Keio Univ.) |
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Speaker |
Author-1 |
Date Time |
2009-09-17 16:05:00 |
Presentation Time |
25 minutes |
Registration for |
RECONF |
Paper # |
RECONF2009-26 |
Volume (vol) |
vol.109 |
Number (no) |
no.198 |
Page |
pp.43-48 |
#Pages |
6 |
Date of Issue |
2009-09-10 (RECONF) |
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