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Paper Abstract and Keywords
Presentation 2009-07-16 11:25
Low Energy Building Design in Packet Buffer Architecture with Deterministic Performance Guarantee
Kazuya Zaitsu (Osaka City Univ.), Hisashi Iwamoto, Yasuto Kuroda, Yuji Yano (Renesas Technology), Koji Yamamoto (Renesas Design), Kazunari Inoue (Renesas Technology), Shingo Ata, Ikuo Oka (Osaka City Univ.) SDM2009-100 ICD2009-16 Link to ES Tech. Rep. Archives: SDM2009-100 ICD2009-16
Abstract (in Japanese) (See Japanese page) 
(in English) To design guaranteed high-performance router, it is problem that packet buffer is non-deterministic. We propose Head Buffer MMU which can realize high-speed data transfer guaranteed packet buffer. Moreover, the MMU can provide large buffers with cost-effective and low power consumption. In this paper, we design the bank selection circuit which can guarantee DRAM high-speed data transfer in Head Buffer MMU. We then show power saving of DRAM by using the bank selection circuit.
Keyword (in Japanese) (See Japanese page) 
(in English) Packet buffer / Rate guarantee / Circuit design / MMU / Head Buffer / / /  
Reference Info. IEICE Tech. Rep., vol. 109, no. 134, ICD2009-16, pp. 17-22, July 2009.
Paper # ICD2009-16 
Date of Issue 2009-07-09 (SDM, ICD) 
ISSN Print edition: ISSN 0913-5685  Online edition: ISSN 2432-6380
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All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF SDM2009-100 ICD2009-16 Link to ES Tech. Rep. Archives: SDM2009-100 ICD2009-16

Conference Information
Committee ICD SDM  
Conference Date 2009-07-16 - 2009-07-17 
Place (in Japanese) (See Japanese page) 
Place (in English) Tokyo Institute of Technology 
Topics (in Japanese) (See Japanese page) 
Topics (in English) Low voltage/low power techniques, novel devices, circuits, and applications 
Paper Information
Registration To ICD 
Conference Code 2009-07-ICD-SDM 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) Low Energy Building Design in Packet Buffer Architecture with Deterministic Performance Guarantee 
Sub Title (in English)  
Keyword(1) Packet buffer  
Keyword(2) Rate guarantee  
Keyword(3) Circuit design  
Keyword(4) MMU  
Keyword(5) Head Buffer  
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1st Author's Name Kazuya Zaitsu  
1st Author's Affiliation Osaka City University (Osaka City Univ.)
2nd Author's Name Hisashi Iwamoto  
2nd Author's Affiliation Renesas Technology (Renesas Technology)
3rd Author's Name Yasuto Kuroda  
3rd Author's Affiliation Renesas Technology (Renesas Technology)
4th Author's Name Yuji Yano  
4th Author's Affiliation Renesas Technology (Renesas Technology)
5th Author's Name Koji Yamamoto  
5th Author's Affiliation Renesas Design (Renesas Design)
6th Author's Name Kazunari Inoue  
6th Author's Affiliation Renesas Technology (Renesas Technology)
7th Author's Name Shingo Ata  
7th Author's Affiliation Osaka City University (Osaka City Univ.)
8th Author's Name Ikuo Oka  
8th Author's Affiliation Osaka City University (Osaka City Univ.)
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Speaker
Date Time 2009-07-16 11:25:00 
Presentation Time 25 
Registration for ICD 
Paper # IEICE-SDM2009-100,IEICE-ICD2009-16 
Volume (vol) IEICE-109 
Number (no) no.133(SDM), no.134(ICD) 
Page pp.17-22 
#Pages IEICE-6 
Date of Issue IEICE-SDM-2009-07-09,IEICE-ICD-2009-07-09 


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