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| Presentation | 2009-06-24 16:30 Design of 30nm FinFET with Halo Structure Tetsuo Endoh, Koji Sakui, Yukio Yasuda (Tohoku Univ../JST-CREST)  ED2009-64 SDM2009-59 Link to ES Tech. Rep. Archives: ED2009-64 SDM2009-59 |
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| Abstract | (in Japanese) | (See Japanese page) |
| (in English) | Design of 30nm FinFETs with halo structure for suppressing the threshold voltage roll-off and improving the subthreshold swing at the same time is proposed for the first time. The performances of nano scale FinFETs with halo structure are analyzed using a two-dimensional device simulator. The device characteristics, focusing especially on the threshold voltage and subthreshold slope, are investigated for different gate length, body thickness, and halo impurity concentration. From the viewpoint of body potential control, it is made clear on how to design the halo structure to suppress the short channel effects and improve the subthreshold-slope. It is shown that by introducing the halo structure to FinFETs, nano-scale FinFETs achieves an improved S-factor and suppressed Vth roll-off simultaneously. | |
| Keyword | (in Japanese) | (See Japanese page) |
| (in English) | FinFET / Halo I/I / MOSFET / threshold voltage roll-off / S-factor / device design / / | |
| Reference Info. | IEICE Tech. Rep., vol. 109, no. 98, SDM2009-59, pp. 63-66, June 2009. | |
| Paper # | SDM2009-59 | |
| Date of Issue | 2009-06-17 (ED, SDM) | |
| ISSN | Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 | |
| Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) | |
| Download PDF | ED2009-64 SDM2009-59 Link to ES Tech. Rep. Archives: ED2009-64 SDM2009-59 |
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| Conference Information | |
| Committee | SDM ED |
| Conference Date | 2009-06-24 - 2009-06-26 |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | Haeundae Grand Hotel, Busan, Korea |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | 2009 Asia-Pacific Workshop on Fundamentals and Applications of Advanced Semiconductor Devices |
| Paper Information | |
| Registration To | SDM |
| Conference Code | 2009-06-SDM-ED |
| Language | English |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Design of 30nm FinFET with Halo Structure |
| Sub Title (in English) | |
| Keyword(1) | FinFET |
| Keyword(2) | Halo I/I |
| Keyword(3) | MOSFET |
| Keyword(4) | threshold voltage roll-off |
| Keyword(5) | S-factor |
| Keyword(6) | device design |
| Keyword(7) | |
| Keyword(8) | |
| 1st Author's Name | Tetsuo Endoh |
| 1st Author's Affiliation | Tohoku University/CREST,Japan Science and Technology Agency (Tohoku Univ../JST-CREST) |
| 2nd Author's Name | Koji Sakui |
| 2nd Author's Affiliation | Tohoku University/CREST,Japan Science and Technology Agency (Tohoku Univ../JST-CREST) |
| 3rd Author's Name | Yukio Yasuda |
| 3rd Author's Affiliation | Tohoku University/CREST,Japan Science and Technology Agency (Tohoku Univ../JST-CREST) |
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| Speaker | Author-1 |
| Date Time | 2009-06-24 16:30:00 |
| Presentation Time | 15 minutes |
| Registration for | SDM |
| Paper # | ED2009-64, SDM2009-59 |
| Volume (vol) | vol.109 |
| Number (no) | no.97(ED), no.98(SDM) |
| Page | pp.63-66 |
| #Pages | 4 |
| Date of Issue | 2009-06-17 (ED, SDM) |
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