IEICE Technical Committee Submission System
Conference Paper's Information
Online Proceedings
[Sign in]
Tech. Rep. Archives
 Go Top Page Go Previous   [Japanese] / [English] 

Paper Abstract and Keywords
Presentation 2009-06-24 15:15
Study of the DC Performance of Fabricated Magnetic Tunnel Junction Integrated on Back-end Metal Line of CMOS Circuits
Fumitaka Iga, Masashi Kamiyanagi, Shoji Ikeda (Tohoku Univ.), Katsuya Miura (Tohoku Univ./Hitachi), Jun Hayakawa (Hitachi), Haruhiro Hasegawa, Takahiro Hanyu, Hideo Ohno, Tetsuo Endoh (Tohoku Univ.) ED2009-53 SDM2009-48 Link to ES Tech. Rep. Archives: ED2009-53 SDM2009-48
Abstract (in Japanese) (See Japanese page) 
(in English) In this paper, we have succeeded in the fabrication of high performance Magnetic Tunnel Junction (MTJ) which is integrated in CMOS circuit with 4-Metal / 1-poly Gate 0.14${\rm \mu}$m CMOS process. We have measured the DC characteristics of the MTJ that is fabricated on via metal of 3rd layer metal line.This MTJ of 60x180${\rm nm^2}$ achieves a large change in resistance of 3.52k${\rm \Omega}$ (anti-parallel) with TMR ratio of 151% at room temperature, which is large enough for sensing scheme of standard CMOS logic. Furthermore, the write current is 320${\rm \mu}$A that can be driven by a standard MOS transistor. As the results, it is shown that the DC performance of our fabricated MTJ integrated in CMOS circuits is very good for our novel spin logic (MTJ-based logic) device.
Keyword (in Japanese) (See Japanese page) 
(in English) magnetic tunnel junction (MTJ) / spin-transfer torque RAM (STT-RAM) / memory-in-logic / MgO barrier / spintronics / tunnel magnetoresistance (TMR) / magnetoresistive RAM (MRAM) / current induced magnetization switching  
Reference Info. IEICE Tech. Rep., vol. 109, no. 98, SDM2009-48, pp. 13-16, June 2009.
Paper # SDM2009-48 
Date of Issue 2009-06-17 (ED, SDM) 
ISSN Print edition: ISSN 0913-5685    Online edition: ISSN 2432-6380
Copyright
and
reproduction
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF ED2009-53 SDM2009-48 Link to ES Tech. Rep. Archives: ED2009-53 SDM2009-48

Conference Information
Committee SDM ED  
Conference Date 2009-06-24 - 2009-06-26 
Place (in Japanese) (See Japanese page) 
Place (in English) Haeundae Grand Hotel, Busan, Korea 
Topics (in Japanese) (See Japanese page) 
Topics (in English) 2009 Asia-Pacific Workshop on Fundamentals and Applications of Advanced Semiconductor Devices 
Paper Information
Registration To SDM 
Conference Code 2009-06-SDM-ED 
Language English 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) Study of the DC Performance of Fabricated Magnetic Tunnel Junction Integrated on Back-end Metal Line of CMOS Circuits 
Sub Title (in English)  
Keyword(1) magnetic tunnel junction (MTJ)  
Keyword(2) spin-transfer torque RAM (STT-RAM)  
Keyword(3) memory-in-logic  
Keyword(4) MgO barrier  
Keyword(5) spintronics  
Keyword(6) tunnel magnetoresistance (TMR)  
Keyword(7) magnetoresistive RAM (MRAM)  
Keyword(8) current induced magnetization switching  
1st Author's Name Fumitaka Iga  
1st Author's Affiliation Tohoku University (Tohoku Univ.)
2nd Author's Name Masashi Kamiyanagi  
2nd Author's Affiliation Tohoku University (Tohoku Univ.)
3rd Author's Name Shoji Ikeda  
3rd Author's Affiliation Tohoku University (Tohoku Univ.)
4th Author's Name Katsuya Miura  
4th Author's Affiliation Tohoku University/Hitachi Advanced Research Laboratory (Tohoku Univ./Hitachi)
5th Author's Name Jun Hayakawa  
5th Author's Affiliation Hitachi Advanced Research Laboratory (Hitachi)
6th Author's Name Haruhiro Hasegawa  
6th Author's Affiliation Tohoku University (Tohoku Univ.)
7th Author's Name Takahiro Hanyu  
7th Author's Affiliation Tohoku University (Tohoku Univ.)
8th Author's Name Hideo Ohno  
8th Author's Affiliation Tohoku University (Tohoku Univ.)
9th Author's Name Tetsuo Endoh  
9th Author's Affiliation Tohoku University (Tohoku Univ.)
10th Author's Name  
10th Author's Affiliation ()
11th Author's Name  
11th Author's Affiliation ()
12th Author's Name  
12th Author's Affiliation ()
13th Author's Name  
13th Author's Affiliation ()
14th Author's Name  
14th Author's Affiliation ()
15th Author's Name  
15th Author's Affiliation ()
16th Author's Name  
16th Author's Affiliation ()
17th Author's Name  
17th Author's Affiliation ()
18th Author's Name  
18th Author's Affiliation ()
19th Author's Name  
19th Author's Affiliation ()
20th Author's Name  
20th Author's Affiliation ()
Speaker Author-1 
Date Time 2009-06-24 15:15:00 
Presentation Time 15 minutes 
Registration for SDM 
Paper # ED2009-53, SDM2009-48 
Volume (vol) vol.109 
Number (no) no.97(ED), no.98(SDM) 
Page pp.13-16 
#Pages
Date of Issue 2009-06-17 (ED, SDM) 


[Return to Top Page]

[Return to IEICE Web Page]


The Institute of Electronics, Information and Communication Engineers (IEICE), Japan