Paper Abstract and Keywords |
Presentation |
2009-06-24 15:15
Study of the DC Performance of Fabricated Magnetic Tunnel Junction Integrated on Back-end Metal Line of CMOS Circuits Fumitaka Iga, Masashi Kamiyanagi, Shoji Ikeda (Tohoku Univ.), Katsuya Miura (Tohoku Univ./Hitachi), Jun Hayakawa (Hitachi), Haruhiro Hasegawa, Takahiro Hanyu, Hideo Ohno, Tetsuo Endoh (Tohoku Univ.) ED2009-53 SDM2009-48 Link to ES Tech. Rep. Archives: ED2009-53 SDM2009-48 |
Abstract |
(in Japanese) |
(See Japanese page) |
(in English) |
In this paper, we have succeeded in the fabrication of high performance Magnetic Tunnel Junction (MTJ) which is integrated in CMOS circuit with 4-Metal / 1-poly Gate 0.14${\rm \mu}$m CMOS process. We have measured the DC characteristics of the MTJ that is fabricated on via metal of 3rd layer metal line.This MTJ of 60x180${\rm nm^2}$ achieves a large change in resistance of 3.52k${\rm \Omega}$ (anti-parallel) with TMR ratio of 151% at room temperature, which is large enough for sensing scheme of standard CMOS logic. Furthermore, the write current is 320${\rm \mu}$A that can be driven by a standard MOS transistor. As the results, it is shown that the DC performance of our fabricated MTJ integrated in CMOS circuits is very good for our novel spin logic (MTJ-based logic) device. |
Keyword |
(in Japanese) |
(See Japanese page) |
(in English) |
magnetic tunnel junction (MTJ) / spin-transfer torque RAM (STT-RAM) / memory-in-logic / MgO barrier / spintronics / tunnel magnetoresistance (TMR) / magnetoresistive RAM (MRAM) / current induced magnetization switching |
Reference Info. |
IEICE Tech. Rep., vol. 109, no. 98, SDM2009-48, pp. 13-16, June 2009. |
Paper # |
SDM2009-48 |
Date of Issue |
2009-06-17 (ED, SDM) |
ISSN |
Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 |
Copyright and reproduction |
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ED2009-53 SDM2009-48 Link to ES Tech. Rep. Archives: ED2009-53 SDM2009-48 |
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