Paper Abstract and Keywords |
Presentation |
2009-06-19 10:20
Design method of easily testable parallel prefix adders Hidetoshi Suzuki, Naofumi Takagi (Nagoya Univ) DC2009-10 |
Abstract |
(in Japanese) |
(See Japanese page) |
(in English) |
We propose a design method of easily testable parallel prefix adders. In a parallel prefix adder, the prefix computation, i.e., computation of carry generation and propagation condition from the least significant position to each bit position is performed in parallel. There are several onfigurations of the prefix computation circuit, and hence, we can design a parallel prefix adder that fits a given requirement on the computation time, area etc. We can design an n-bit adder which can be tested with 24n-2 patterns under the cell fault model, by introducing an additional input line and modifying the functions of the cells of four kinds. |
Keyword |
(in Japanese) |
(See Japanese page) |
(in English) |
Design for testability / parallel prefix adder / / / / / / |
Reference Info. |
IEICE Tech. Rep., vol. 109, no. 95, DC2009-10, pp. 1-6, June 2009. |
Paper # |
DC2009-10 |
Date of Issue |
2009-06-12 (DC) |
ISSN |
Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 |
Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) |
Download PDF |
DC2009-10 |
Conference Information |
Committee |
DC |
Conference Date |
2009-06-19 - 2009-06-19 |
Place (in Japanese) |
(See Japanese page) |
Place (in English) |
Kikai-Shinko-Kaikan Bldg. |
Topics (in Japanese) |
(See Japanese page) |
Topics (in English) |
Design, Test, Verification |
Paper Information |
Registration To |
DC |
Conference Code |
2009-06-DC |
Language |
Japanese |
Title (in Japanese) |
(See Japanese page) |
Sub Title (in Japanese) |
(See Japanese page) |
Title (in English) |
Design method of easily testable parallel prefix adders |
Sub Title (in English) |
|
Keyword(1) |
Design for testability |
Keyword(2) |
parallel prefix adder |
Keyword(3) |
|
Keyword(4) |
|
Keyword(5) |
|
Keyword(6) |
|
Keyword(7) |
|
Keyword(8) |
|
1st Author's Name |
Hidetoshi Suzuki |
1st Author's Affiliation |
Nagoya Univesity (Nagoya Univ) |
2nd Author's Name |
Naofumi Takagi |
2nd Author's Affiliation |
Nagoya Univesity (Nagoya Univ) |
3rd Author's Name |
|
3rd Author's Affiliation |
() |
4th Author's Name |
|
4th Author's Affiliation |
() |
5th Author's Name |
|
5th Author's Affiliation |
() |
6th Author's Name |
|
6th Author's Affiliation |
() |
7th Author's Name |
|
7th Author's Affiliation |
() |
8th Author's Name |
|
8th Author's Affiliation |
() |
9th Author's Name |
|
9th Author's Affiliation |
() |
10th Author's Name |
|
10th Author's Affiliation |
() |
11th Author's Name |
|
11th Author's Affiliation |
() |
12th Author's Name |
|
12th Author's Affiliation |
() |
13th Author's Name |
|
13th Author's Affiliation |
() |
14th Author's Name |
|
14th Author's Affiliation |
() |
15th Author's Name |
|
15th Author's Affiliation |
() |
16th Author's Name |
|
16th Author's Affiliation |
() |
17th Author's Name |
|
17th Author's Affiliation |
() |
18th Author's Name |
|
18th Author's Affiliation |
() |
19th Author's Name |
|
19th Author's Affiliation |
() |
20th Author's Name |
|
20th Author's Affiliation |
() |
Speaker |
Author-1 |
Date Time |
2009-06-19 10:20:00 |
Presentation Time |
25 minutes |
Registration for |
DC |
Paper # |
DC2009-10 |
Volume (vol) |
vol.109 |
Number (no) |
no.95 |
Page |
pp.1-6 |
#Pages |
6 |
Date of Issue |
2009-06-12 (DC) |
|