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Paper Abstract and Keywords
Presentation 2009-06-12 10:35
VLSI Design of a Dynamic Reconfigurable MMSE Detector for 4x4 MIMO-OFDM Receiver
Hirokazu Ikeuchi, Shingo Yoshizawa, Yoshikazu Miyanaga (Hokkaido Univ.) SIS2009-14
Abstract (in Japanese) (See Japanese page) 
(in English) This report presents a VLSI architecture of dynamic reconfigurable MMSE detection in a 4x4 MIMO-OFDM receiver. MIMO-OFDM imposes requirement of fast computing on the matrix inversion and small circuit area because of strict timing in frame structure and subcarrier-by-subcarrier basis processing. We propose a technique to optimize arithmetic units in the allowed time of pipelined MMSE detector by adopting a dynamic reconfigurable architecture to compute Strassen's algorithms of matrix inversion and multiplication. The proposed technique achieves large reduction of circuit area and power consumption. The designed circuit has been implemented to a 90-nm CMOS process and evaluated in processing latency, circuit area and power consumption.
Keyword (in Japanese) (See Japanese page) 
(in English) MIMO-OFDM / MIMO Decoder / MMSE Detection / Dynamic Reconfigurable / VLSI Architecture / / /  
Reference Info. IEICE Tech. Rep., vol. 109, no. 78, SIS2009-14, pp. 79-84, June 2009.
Paper # SIS2009-14 
Date of Issue 2009-06-04 (SIS) 
ISSN Print edition: ISSN 0913-5685  Online edition: ISSN 2432-6380
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF SIS2009-14

Conference Information
Committee SIS  
Conference Date 2009-06-11 - 2009-06-12 
Place (in Japanese) (See Japanese page) 
Place (in English)  
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Paper Information
Registration To SIS 
Conference Code 2009-06-SIS 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) VLSI Design of a Dynamic Reconfigurable MMSE Detector for 4x4 MIMO-OFDM Receiver 
Sub Title (in English)  
Keyword(1) MIMO-OFDM  
Keyword(2) MIMO Decoder  
Keyword(3) MMSE Detection  
Keyword(4) Dynamic Reconfigurable  
Keyword(5) VLSI Architecture  
1st Author's Name Hirokazu Ikeuchi  
1st Author's Affiliation Hokkaido University (Hokkaido Univ.)
2nd Author's Name Shingo Yoshizawa  
2nd Author's Affiliation Hokkaido University (Hokkaido Univ.)
3rd Author's Name Yoshikazu Miyanaga  
3rd Author's Affiliation Hokkaido University (Hokkaido Univ.)
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Date Time 2009-06-12 10:35:00 
Presentation Time 25 
Registration for SIS 
Paper # IEICE-SIS2009-14 
Volume (vol) IEICE-109 
Number (no) no.78 
Page pp.79-84 
#Pages IEICE-6 
Date of Issue IEICE-SIS-2009-06-04 

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