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| Presentation | 2009-05-20 15:20 A scan test generation method to reduce the number of detected untestable faults Hiroshi Ogawa (Nihon Univ.), Masayoshi Yoshimura (Kyushu Univ.), Toshinori Hosokawa (Nihon Univ.), Koji Yamazaki (Meiji Univ.)  VLD2009-3 |
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| Abstract | (in Japanese) | (See Japanese page) |
| (in English) | There are faults which can be detected by only the invalid test patterns. This is one of the causes for the overtesting. Overtesting occurs that faults on a chip are detected under invalid states using scan chains. However it is difficult to find all invalid states based on circuit structures. On the other hand, untestable faults identification can be used sequential ATPG based on time expansion models. The our proposed method is composed of generating multi cycle capture test patterns, identifying untestable faults and extracting single cycle capture patterns from multi cycle capture sequences to reduce the number of detection for untestable faults. | |
| Keyword | (in Japanese) | (See Japanese page) |
| (in English) | untestable fault / k cycle capture test pattern generation / scan design / time expansion model / / / / | |
| Reference Info. | IEICE Tech. Rep., vol. 109, no. 34, VLD2009-3, pp. 13-18, May 2009. | |
| Paper # | VLD2009-3 | |
| Date of Issue | 2009-05-13 (VLD) | |
| ISSN | Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 | |
| Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) | |
| Download PDF | VLD2009-3 |
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| Conference Information | |
| Committee | VLD IPSJ-SLDM |
| Conference Date | 2009-05-20 - 2009-05-21 |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | Kitakyushu International Conference Center |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | System Design, etc. |
| Paper Information | |
| Registration To | VLD |
| Conference Code | 2009-05-VLD-SLDM |
| Language | Japanese |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | A scan test generation method to reduce the number of detected untestable faults |
| Sub Title (in English) | |
| Keyword(1) | untestable fault |
| Keyword(2) | k cycle capture test pattern generation |
| Keyword(3) | scan design |
| Keyword(4) | time expansion model |
| Keyword(5) | |
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| 1st Author's Name | Hiroshi Ogawa |
| 1st Author's Affiliation | Nihon University (Nihon Univ.) |
| 2nd Author's Name | Masayoshi Yoshimura |
| 2nd Author's Affiliation | Kyushu University (Kyushu Univ.) |
| 3rd Author's Name | Toshinori Hosokawa |
| 3rd Author's Affiliation | Nihon University (Nihon Univ.) |
| 4th Author's Name | Koji Yamazaki |
| 4th Author's Affiliation | Meiji University (Meiji Univ.) |
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| Speaker | Author-1 |
| Date Time | 2009-05-20 15:20:00 |
| Presentation Time | 25 minutes |
| Registration for | VLD |
| Paper # | VLD2009-3 |
| Volume (vol) | vol.109 |
| Number (no) | no.34 |
| Page | pp.13-18 |
| #Pages | 6 |
| Date of Issue | 2009-05-13 (VLD) |
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