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| Presentation | 2009-05-15 11:00 Development and Evaluation of Cryptographic Hardware Generated by Behavior-level Synthesis Yohei Hori, Mai Itoh (Chuo Univ.), Hideki Imai (Chuo Univ./AIST)  RECONF2009-12 |
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| Abstract | (in Japanese) | (See Japanese page) |
| (in English) | Cryptography is widely applied to various consumer electronics to protect digital contents, users' privacy, product confidentiality and so on. However, the development period of cryptographic hardware is exceedingly longer than that of software. Behavior-level synthesis could solve this problem, nevertheless its effectiveness is vague so far. This paper reveals the feasibility of behavior-level synthesis for the development of cryptographic hardware and discusses the optimal coding scheme to achieve high-performance hardware. |
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| Keyword | (in Japanese) | (See Japanese page) |
| (in English) | behavior-level synthesis / cryptographic hadware / FPGA / AES / / / / | |
| Reference Info. | IEICE Tech. Rep., vol. 109, no. 26, RECONF2009-12, pp. 67-72, May 2009. | |
| Paper # | RECONF2009-12 | |
| Date of Issue | 2009-05-07 (RECONF) | |
| ISSN | Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 | |
| Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) | |
| Download PDF | RECONF2009-12 |
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| Conference Information | |
| Committee | RECONF |
| Conference Date | 2009-05-14 - 2009-05-15 |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
| Paper Information | |
| Registration To | RECONF |
| Conference Code | 2009-05-RECONF |
| Language | Japanese |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Development and Evaluation of Cryptographic Hardware Generated by Behavior-level Synthesis |
| Sub Title (in English) | |
| Keyword(1) | behavior-level synthesis |
| Keyword(2) | cryptographic hadware |
| Keyword(3) | FPGA |
| Keyword(4) | AES |
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| 1st Author's Name | Yohei Hori |
| 1st Author's Affiliation | Chuo University (Chuo Univ.) |
| 2nd Author's Name | Mai Itoh |
| 2nd Author's Affiliation | Chuo University (Chuo Univ.) |
| 3rd Author's Name | Hideki Imai |
| 3rd Author's Affiliation | Chuo University/National Institute of Advanced Industrial Science and Tecnology (Chuo Univ./AIST) |
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| Speaker | Author-1 |
| Date Time | 2009-05-15 11:00:00 |
| Presentation Time | 30 minutes |
| Registration for | RECONF |
| Paper # | RECONF2009-12 |
| Volume (vol) | vol.109 |
| Number (no) | no.26 |
| Page | pp.67-72 |
| #Pages | 6 |
| Date of Issue | 2009-05-07 (RECONF) |
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