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Paper Abstract and Keywords
Presentation 2009-05-14 14:30
A Power of FPGA Reduction Using FPGA Routing Structure Based on the Small-World Network
Shoichi Nishida (Kumamoto Univ.), Yuzo Nishioka (Hitachi-Omron Terminal Solutions, Corp.), Motoki Amagasaki, Masahiro Iida, Toshinori Sueyoshi (Kumamoto Univ.) RECONF2009-4
Abstract (in Japanese) (See Japanese page) 
(in English) The performance of field-programmable gate arrays(FPGA) has improved dramatically owing to new process technology. But, FPGA has a lot of problem in new process technology. Particularly, the issue of FPGA's power consumption is serious because FPGA have a lot of routing resources. We propose to apply the small-wrold network to the routing structure of FPGA's for the power issue. As the small-world routing structure has not a few low-load shortcut lines. The shortcut lines decrease the average number of node-to-node steps. we take advantage of these lines for the high activity paths of circuit. As a result the average power is decreased 8\% as composed with a conventional routing structure.
Keyword (in Japanese) (See Japanese page) 
(in English) FPGA / small-world network / low power / routing structure / / / /  
Reference Info. IEICE Tech. Rep., vol. 109, no. 26, RECONF2009-4, pp. 19-24, May 2009.
Paper # RECONF2009-4 
Date of Issue 2009-05-07 (RECONF) 
ISSN Print edition: ISSN 0913-5685    Online edition: ISSN 2432-6380
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All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
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Conference Information
Committee RECONF  
Conference Date 2009-05-14 - 2009-05-15 
Place (in Japanese) (See Japanese page) 
Place (in English)  
Topics (in Japanese) (See Japanese page) 
Topics (in English)  
Paper Information
Registration To RECONF 
Conference Code 2009-05-RECONF 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) A Power of FPGA Reduction Using FPGA Routing Structure Based on the Small-World Network 
Sub Title (in English)  
Keyword(1) FPGA  
Keyword(2) small-world network  
Keyword(3) low power  
Keyword(4) routing structure  
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1st Author's Name Shoichi Nishida  
1st Author's Affiliation Kumamoto University (Kumamoto Univ.)
2nd Author's Name Yuzo Nishioka  
2nd Author's Affiliation Hitachi-Omron Terminal Solutions, Corp (Hitachi-Omron Terminal Solutions, Corp.)
3rd Author's Name Motoki Amagasaki  
3rd Author's Affiliation Kumamoto University (Kumamoto Univ.)
4th Author's Name Masahiro Iida  
4th Author's Affiliation Kumamoto University (Kumamoto Univ.)
5th Author's Name Toshinori Sueyoshi  
5th Author's Affiliation Kumamoto University (Kumamoto Univ.)
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Speaker Author-1 
Date Time 2009-05-14 14:30:00 
Presentation Time 30 minutes 
Registration for RECONF 
Paper # RECONF2009-4 
Volume (vol) vol.109 
Number (no) no.26 
Page pp.19-24 
#Pages
Date of Issue 2009-05-07 (RECONF) 


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