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| Presentation | 2009-05-14 13:30 Real Chip Evaluation of Dynamically Reconfigurable Processor Array MuCCRA-3 Yoshihiro Yasuda, Yoshiki Saito, Toru Sano, Masaru Kato, Hideharu Amano (Keio Univ.)  RECONF2009-2 |
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| Abstract | (in Japanese) | (See Japanese page) |
| (in English) | Dynamically Reconfigurable Processor Array(DRPA) has been received an attention as a flexible and power efficient off-loading engine for embedded devices. MuCCRA, our original DRPA, has been developed to research on the methond for lowering its power consumption. In this paper, the third prototype chip MuCCRA-3 is introduced. As a result of evaluation, MuCCRA-3 has 30 times better energy efficiency than MuCCRA-1, implemented with 180nm process, and 200 times than the DSP with 130nm process. | |
| Keyword | (in Japanese) | (See Japanese page) |
| (in English) | Dynamically Reconfigurable Processor Array / Real Chip / / / / / / | |
| Reference Info. | IEICE Tech. Rep., vol. 109, no. 26, RECONF2009-2, pp. 7-12, May 2009. | |
| Paper # | RECONF2009-2 | |
| Date of Issue | 2009-05-07 (RECONF) | |
| ISSN | Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 | |
| Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) | |
| Download PDF | RECONF2009-2 |
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| Conference Information | |
| Committee | RECONF |
| Conference Date | 2009-05-14 - 2009-05-15 |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
| Paper Information | |
| Registration To | RECONF |
| Conference Code | 2009-05-RECONF |
| Language | Japanese |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Real Chip Evaluation of Dynamically Reconfigurable Processor Array MuCCRA-3 |
| Sub Title (in English) | |
| Keyword(1) | Dynamically Reconfigurable Processor Array |
| Keyword(2) | Real Chip |
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| 1st Author's Name | Yoshihiro Yasuda |
| 1st Author's Affiliation | Keio University (Keio Univ.) |
| 2nd Author's Name | Yoshiki Saito |
| 2nd Author's Affiliation | Keio University (Keio Univ.) |
| 3rd Author's Name | Toru Sano |
| 3rd Author's Affiliation | Keio University (Keio Univ.) |
| 4th Author's Name | Masaru Kato |
| 4th Author's Affiliation | Keio University (Keio Univ.) |
| 5th Author's Name | Hideharu Amano |
| 5th Author's Affiliation | Keio University (Keio Univ.) |
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| Speaker | Author-1 |
| Date Time | 2009-05-14 13:30:00 |
| Presentation Time | 30 minutes |
| Registration for | RECONF |
| Paper # | RECONF2009-2 |
| Volume (vol) | vol.109 |
| Number (no) | no.26 |
| Page | pp.7-12 |
| #Pages | 6 |
| Date of Issue | 2009-05-07 (RECONF) |
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