Paper Abstract and Keywords |
Presentation |
2009-04-14 10:40
A 0.56-V 128kb 10T SRAM Using Column Line Assist (CLA) Scheme Shusuke Yoshimoto, Yusuke Iguchi, Shunsuke Okumura, Hidehiro Fujiwara, Hiroki Noguchi (Kobe Univ.), Koji Nii (Renesas Technology Corp.), Hiroshi Kawaguchi, Masahiko Yoshimoto (Kobe Univ.) ICD2009-6 Link to ES Tech. Rep. Archives: ICD2009-6 |
Abstract |
(in Japanese) |
(See Japanese page) |
(in English) |
We present a small-area 10T SRAM cell without half selection problem. As well, the proposed 10T cell achieves a faster access time and low voltage operation. The cell area is reduced by 25%, and the cell current is increased by 21%, compared with the prior 10T cell. The minimum operating voltage is lowered by the column line assist (CLA) scheme that suppresses write margin degradation. By measurement, we confirmed that the proposed 128-kb SRAM works at 0.56 V. |
Keyword |
(in Japanese) |
(See Japanese page) |
(in English) |
SRAM / low voltage operation / small area / 10 transistor / 10T / Column line assist / / |
Reference Info. |
IEICE Tech. Rep., vol. 109, no. 2, ICD2009-6, pp. 27-32, April 2009. |
Paper # |
ICD2009-6 |
Date of Issue |
2009-04-06 (ICD) |
ISSN |
Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 |
Copyright and reproduction |
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ICD2009-6 Link to ES Tech. Rep. Archives: ICD2009-6 |
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