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| Presentation | 2009-03-13 11:30 Decoupling Capacitance Allocation for Timing with Statistical Noise Model and Timing Analysis Takashi Enami, Masanori Hashimoto (Osaka Univ.), Takashi Sato (Tokyo Inst. of Tech.)  VLD2008-161 |
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| Abstract | (in Japanese) | (See Japanese page) |
| (in English) | This paper presents an allocation method of decoupling capacitance that explicitly considers timing. We have found and focused that decap does not necessarily improve a gate delay at all the switching timing within a cycle, and devised an efficient sensitivity calculation of timing to decap for decap allocation. The proposed method, which is based on a statistical noise modeling and timing analysis, accelerates the sensitivity calculation with an approximation and adjoint sensitivity analysis. Experimental results show that the decap allocation based on the sensitivity analysis efficiently optimizes the worst-case circuit delay within a given decap budget. Compared to the maximum decap placement, the delay improvement due to decap increases by 5% even while the total amount of decap is reduced to 40%. |
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| Keyword | (in Japanese) | (See Japanese page) |
| (in English) | Decoupling capacitance / Timing improvement / Statistical timing analysis / Adjoint sensitivity analysis / Criticality / / / | |
| Reference Info. | IEICE Tech. Rep., vol. 108, no. 478, VLD2008-161, pp. 207-212, March 2009. | |
| Paper # | VLD2008-161 | |
| Date of Issue | 2009-03-04 (VLD) | |
| ISSN | Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 | |
| Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) | |
| Download PDF | VLD2008-161 |
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| Conference Information | |
| Committee | VLD |
| Conference Date | 2009-03-11 - 2009-03-13 |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | Design Technology for a System-on-Silicon |
| Paper Information | |
| Registration To | VLD |
| Conference Code | 2009-03-VLD |
| Language | Japanese |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Decoupling Capacitance Allocation for Timing with Statistical Noise Model and Timing Analysis |
| Sub Title (in English) | |
| Keyword(1) | Decoupling capacitance |
| Keyword(2) | Timing improvement |
| Keyword(3) | Statistical timing analysis |
| Keyword(4) | Adjoint sensitivity analysis |
| Keyword(5) | Criticality |
| Keyword(6) | |
| Keyword(7) | |
| Keyword(8) | |
| 1st Author's Name | Takashi Enami |
| 1st Author's Affiliation | Osaka University (Osaka Univ.) |
| 2nd Author's Name | Masanori Hashimoto |
| 2nd Author's Affiliation | Osaka University (Osaka Univ.) |
| 3rd Author's Name | Takashi Sato |
| 3rd Author's Affiliation | Tokyo Institute of Technology (Tokyo Inst. of Tech.) |
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| Speaker | Author-1 |
| Date Time | 2009-03-13 11:30:00 |
| Presentation Time | 25 minutes |
| Registration for | VLD |
| Paper # | VLD2008-161 |
| Volume (vol) | vol.108 |
| Number (no) | no.478 |
| Page | pp.207-212 |
| #Pages | 6 |
| Date of Issue | 2009-03-04 (VLD) |
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