Paper Abstract and Keywords |
Presentation |
2009-03-12 13:25
A Proposal of an Adaptive Network on Chip for Multi-Core SoC Hiroshi Kadota (Kyushu Univ.), Akiyoshi Wakatani (Konan Univ) VLD2008-146 |
Abstract |
(in Japanese) |
(See Japanese page) |
(in English) |
The Network-on-Chip (NoC) for today’s multi/many-core architecture should be evaluated by its power dissipation rather than its hardware cost. This situation allows us to design a topology-adaptive NoC, which we will propose here, according to the transfer modes with some additional hardware. In the intelligent image parallel processing, for example, two types of data-transfer modes, local and global, are used, and our proposed NoC would support the former mode with pure torus structure and the latter mode with Clos-torus mixed structure by changing its configuration. The initial studies of the transfer operations are performed by a simplified simulation. The latencies and power dissipation are estimated on two types of structure for two types of transfer modes respectively. In our Clos-torus mixture network, 16-I/O-node Clos-network blocks are embedded in the 4 rows x 4 column global torus network, which reduce the latencies by half but increase the power dissipation. The selective usage of these two types of the structures could realize the optimum operations from performance/power view points. These initial studies will be described in this manuscript. |
Keyword |
(in Japanese) |
(See Japanese page) |
(in English) |
Network-on-Chip / Torus Network / Clos Network / Network Topology / / / / |
Reference Info. |
IEICE Tech. Rep., vol. 108, no. 478, VLD2008-146, pp. 117-122, March 2009. |
Paper # |
VLD2008-146 |
Date of Issue |
2009-03-04 (VLD) |
ISSN |
Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 |
Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) |
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VLD2008-146 |
Conference Information |
Committee |
VLD |
Conference Date |
2009-03-11 - 2009-03-13 |
Place (in Japanese) |
(See Japanese page) |
Place (in English) |
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Topics (in Japanese) |
(See Japanese page) |
Topics (in English) |
Design Technology for a System-on-Silicon |
Paper Information |
Registration To |
VLD |
Conference Code |
2009-03-VLD |
Language |
Japanese |
Title (in Japanese) |
(See Japanese page) |
Sub Title (in Japanese) |
(See Japanese page) |
Title (in English) |
A Proposal of an Adaptive Network on Chip for Multi-Core SoC |
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Network-on-Chip |
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Torus Network |
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Clos Network |
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Network Topology |
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1st Author's Name |
Hiroshi Kadota |
1st Author's Affiliation |
Kyushu University (Kyushu Univ.) |
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Akiyoshi Wakatani |
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Konan University (Konan Univ) |
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Speaker |
Author-1 |
Date Time |
2009-03-12 13:25:00 |
Presentation Time |
25 minutes |
Registration for |
VLD |
Paper # |
VLD2008-146 |
Volume (vol) |
vol.108 |
Number (no) |
no.478 |
Page |
pp.117-122 |
#Pages |
6 |
Date of Issue |
2009-03-04 (VLD) |
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