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Paper Abstract and Keywords
Presentation 2009-03-12 09:15
Chip evaluation and implimentation of DES encryption using via-programmable-device VPEX
Masahide Kawarasaki, Tomohiro Nishimoto, Yuuichi Kokushou, Kazuma Kitamura, Shouta Yamada (Ritsumeikan Univ.), Masaya Yoshikawa (Meijyou Univ.), Takeshi Fujino (Ritsumeikan Univ.) VLD2008-139
Abstract (in Japanese) (See Japanese page) 
(in English) We have been studied the via-programmable-device VPEX (Via Programmable logic using EXclusive or array) whose logic element consists of the combination of complex-gate-type EXOR gate and Inverter. 12 kinds of logic functions including all two-input and one-output functions can be programmed by changing via-1 layout. Various kinds of combination logics are configured by changing via-3 layout which controls the connection between LEs. Register (DFF: D Flip Flops) can be realized by using some LEs, so sequential-logic is also programmed in the LE array. In this study, we have designed the test chip which has small-scale circuits using VPEX architecture, and check the operation of each logic functions. We improved the elements of LE and realized the decrease of circuit area. As an example of circuit implementation, we applied VPEX architecture to DES encryption circuit, and evaluated the chip area of VPEX compared to that of Standard Cells.
Keyword (in Japanese) (See Japanese page) 
(in English) Via-programmable-logic / EB direct writing / Exclusive-OR / DES encryption / / / /  
Reference Info. IEICE Tech. Rep., vol. 108, no. 478, VLD2008-139, pp. 77-82, March 2009.
Paper # VLD2008-139 
Date of Issue 2009-03-04 (VLD) 
ISSN Print edition: ISSN 0913-5685  Online edition: ISSN 2432-6380
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF VLD2008-139

Conference Information
Committee VLD  
Conference Date 2009-03-11 - 2009-03-13 
Place (in Japanese) (See Japanese page) 
Place (in English)  
Topics (in Japanese) (See Japanese page) 
Topics (in English) Design Technology for a System-on-Silicon 
Paper Information
Registration To VLD 
Conference Code 2009-03-VLD 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) Chip evaluation and implimentation of DES encryption using via-programmable-device VPEX 
Sub Title (in English)  
Keyword(1) Via-programmable-logic  
Keyword(2) EB direct writing  
Keyword(3) Exclusive-OR  
Keyword(4) DES encryption  
1st Author's Name Masahide Kawarasaki  
1st Author's Affiliation Ritsumeikan University (Ritsumeikan Univ.)
2nd Author's Name Tomohiro Nishimoto  
2nd Author's Affiliation Ritsumeikan University (Ritsumeikan Univ.)
3rd Author's Name Yuuichi Kokushou  
3rd Author's Affiliation Ritsumeikan University (Ritsumeikan Univ.)
4th Author's Name Kazuma Kitamura  
4th Author's Affiliation Ritsumeikan University (Ritsumeikan Univ.)
5th Author's Name Shouta Yamada  
5th Author's Affiliation Ritsumeikan University (Ritsumeikan Univ.)
6th Author's Name Masaya Yoshikawa  
6th Author's Affiliation Meijyou University (Meijyou Univ.)
7th Author's Name Takeshi Fujino  
7th Author's Affiliation Ritsumeikan University (Ritsumeikan Univ.)
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Date Time 2009-03-12 09:15:00 
Presentation Time 25 
Registration for VLD 
Paper # IEICE-VLD2008-139 
Volume (vol) IEICE-108 
Number (no) no.478 
Page pp.77-82 
#Pages IEICE-6 
Date of Issue IEICE-VLD-2009-03-04 

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