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Paper Abstract and Keywords
Presentation 2009-03-12 10:05
Differential Power Analysis of bit-value against cipher implementation on FPGA
Kazuki Okuyama, Kenji Kojima, Yuki Makino, Takeshi Fujino (Ritsumei Univ.) VLD2008-141
Abstract (in Japanese) (See Japanese page) 
(in English) DPA side-channel attack is the encryption-key estimation method by the statistical analysis on circuit consumption power. It is not a difficult experiment using an oscilloscope and a dedicated FPGA (SASEBO) board. The “bit-value type DPA” , in which the value of input or output bit of S-Box is used as selection function, is said to be difficult on the FPGA implementation. So, the “bit-transition type DPA” , in which the transition of register value between different round is used as a selection function, is used in the DPA experiment on a FPGA board. In this study, we report that the “bit-value type DPA” is successfully demonstrated by the method, in which S-Boxes are composed of ASIC-type primitive gates. In addition, the countermeasure against the “bit-transition type DPA” is confirmed by the method, in which the random masking with rest-sequence is applied to the input of S-Box.
Keyword (in Japanese) (See Japanese page) 
(in English) Side Channel Attack / Differential Power Analysis / DPA / FPGA / DES / SASEBO / /  
Reference Info. IEICE Tech. Rep., vol. 108, no. 478, VLD2008-141, pp. 89-94, March 2009.
Paper # VLD2008-141 
Date of Issue 2009-03-04 (VLD) 
ISSN Print edition: ISSN 0913-5685  Online edition: ISSN 2432-6380
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
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Conference Information
Committee VLD  
Conference Date 2009-03-11 - 2009-03-13 
Place (in Japanese) (See Japanese page) 
Place (in English)  
Topics (in Japanese) (See Japanese page) 
Topics (in English) Design Technology for a System-on-Silicon 
Paper Information
Registration To VLD 
Conference Code 2009-03-VLD 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) Differential Power Analysis of bit-value against cipher implementation on FPGA 
Sub Title (in English)  
Keyword(1) Side Channel Attack  
Keyword(2) Differential Power Analysis  
Keyword(3) DPA  
Keyword(4) FPGA  
Keyword(5) DES  
Keyword(6) SASEBO  
1st Author's Name Kazuki Okuyama  
1st Author's Affiliation Ritsumeikan University (Ritsumei Univ.)
2nd Author's Name Kenji Kojima  
2nd Author's Affiliation Ritsumeikan University (Ritsumei Univ.)
3rd Author's Name Yuki Makino  
3rd Author's Affiliation Ritsumeikan University (Ritsumei Univ.)
4th Author's Name Takeshi Fujino  
4th Author's Affiliation Ritsumeikan University (Ritsumei Univ.)
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Date Time 2009-03-12 10:05:00 
Presentation Time 25 
Registration for VLD 
Paper # IEICE-VLD2008-141 
Volume (vol) IEICE-108 
Number (no) no.478 
Page pp.89-94 
#Pages IEICE-6 
Date of Issue IEICE-VLD-2009-03-04 

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