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Paper Abstract and Keywords
Presentation 2009-03-12 16:40
Low Power Deblocking Filter Implementation Method for H.264/AVC
Yoshinori Hayashi, Tomohiro Akita, Tian Song, Takashi Shimamoto (Tokushima Univ.) VLD2008-153
Abstract (in Japanese) (See Japanese page) 
(in English) This paper presents a low power architecture for deblocking filter of the H.264/AVC. Deblocking filtering accounts for from one third to half of the computation complexity of the H.264/AVC decoder. Therefore, the low power architecture for deblocking filter becomes important. In this work, focusing on the redundant processing when the filtering strength is obtained, an early judgment of the filtering strength and an efficient architecture are proposed.Proposed architecture is implemented with FPGA (Xilinx Vertex5). Implementation results show that the number of the gate counts are 15.5K and it can work at over 100MHz. Simulation results show that there are maximum 93.4\% reduction in the calculations of filtering strength. Therefore low power implementation can be achieved with the proposed architecture.
Keyword (in Japanese) (See Japanese page) 
(in English) H.264/AVC / Deblocking Filter / Low power / Architecture / / / /  
Reference Info. IEICE Tech. Rep., vol. 108, no. 478, VLD2008-153, pp. 159-164, March 2009.
Paper # VLD2008-153 
Date of Issue 2009-03-04 (VLD) 
ISSN Print edition: ISSN 0913-5685  Online edition: ISSN 2432-6380
Copyright
and
reproduction
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
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Conference Information
Committee VLD  
Conference Date 2009-03-11 - 2009-03-13 
Place (in Japanese) (See Japanese page) 
Place (in English)  
Topics (in Japanese) (See Japanese page) 
Topics (in English) Design Technology for a System-on-Silicon 
Paper Information
Registration To VLD 
Conference Code 2009-03-VLD 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) Low Power Deblocking Filter Implementation Method for H.264/AVC 
Sub Title (in English)  
Keyword(1) H.264/AVC  
Keyword(2) Deblocking Filter  
Keyword(3) Low power  
Keyword(4) Architecture  
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1st Author's Name Yoshinori Hayashi  
1st Author's Affiliation Tokushima University (Tokushima Univ.)
2nd Author's Name Tomohiro Akita  
2nd Author's Affiliation Tokushima University (Tokushima Univ.)
3rd Author's Name Tian Song  
3rd Author's Affiliation Tokushima University (Tokushima Univ.)
4th Author's Name Takashi Shimamoto  
4th Author's Affiliation Tokushima University (Tokushima Univ.)
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Speaker
Date Time 2009-03-12 16:40:00 
Presentation Time 25 
Registration for VLD 
Paper # IEICE-VLD2008-153 
Volume (vol) IEICE-108 
Number (no) no.478 
Page pp.159-164 
#Pages IEICE-6 
Date of Issue IEICE-VLD-2009-03-04 


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