Paper Abstract and Keywords |
Presentation |
2009-03-12 10:30
A Formal Verification Method for On-Chip Programmable Interconnect Takaaki Tagawa, Hiroaki Yoshida, Masahiro Fujita (Univ. of Tokyo) VLD2008-142 |
Abstract |
(in Japanese) |
(See Japanese page) |
(in English) |
As the development cost increases, programmable devices such as FPGAs are becoming critically important. A key component of such programmable devices is a programmable interconnect. Typically they are designed with full-custom design methodology and hence it is likely to have design errors.
In this paper, we propose a formal verification method for on-chip programmable interconnect at the transistor level. We present a scalability analysis of the proposed method and also demonstrate that the proposed method successfully proves the correctness of an actual VLSI design. |
Keyword |
(in Japanese) |
(See Japanese page) |
(in English) |
Programmable interconenct / formal verification / satisfiability problem / FPGA / / / / |
Reference Info. |
IEICE Tech. Rep., vol. 108, no. 478, VLD2008-142, pp. 95-100, March 2009. |
Paper # |
VLD2008-142 |
Date of Issue |
2009-03-04 (VLD) |
ISSN |
Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 |
Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) |
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VLD2008-142 |
Conference Information |
Committee |
VLD |
Conference Date |
2009-03-11 - 2009-03-13 |
Place (in Japanese) |
(See Japanese page) |
Place (in English) |
|
Topics (in Japanese) |
(See Japanese page) |
Topics (in English) |
Design Technology for a System-on-Silicon |
Paper Information |
Registration To |
VLD |
Conference Code |
2009-03-VLD |
Language |
Japanese |
Title (in Japanese) |
(See Japanese page) |
Sub Title (in Japanese) |
(See Japanese page) |
Title (in English) |
A Formal Verification Method for On-Chip Programmable Interconnect |
Sub Title (in English) |
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Keyword(1) |
Programmable interconenct |
Keyword(2) |
formal verification |
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satisfiability problem |
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FPGA |
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1st Author's Name |
Takaaki Tagawa |
1st Author's Affiliation |
University of Tokyo (Univ. of Tokyo) |
2nd Author's Name |
Hiroaki Yoshida |
2nd Author's Affiliation |
University of Tokyo (Univ. of Tokyo) |
3rd Author's Name |
Masahiro Fujita |
3rd Author's Affiliation |
University of Tokyo (Univ. of Tokyo) |
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Speaker |
Author-1 |
Date Time |
2009-03-12 10:30:00 |
Presentation Time |
25 minutes |
Registration for |
VLD |
Paper # |
VLD2008-142 |
Volume (vol) |
vol.108 |
Number (no) |
no.478 |
Page |
pp.95-100 |
#Pages |
6 |
Date of Issue |
2009-03-04 (VLD) |