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Paper Abstract and Keywords
Presentation 2009-03-11 16:40
A Maximization Method of Parallel Wire Lengths in Routing Area With Lengths in Routing Area with Obstacles
Suguru Suehiro, Yukihide Kohira, Atsushi Takahashi (Tokyo Inst. of Tech.) VLD2008-136
Abstract (in Japanese) (See Japanese page) 
(in English) Due to the speeding up of VLSI systems, the PCB routing design is requested to take signal delay and signal integrity into account. Our goal is to develop a routing method for PCB in which signal delay and signal integrity are taken into account. In this paper, in order to evaluate the routing area which is assigned to differential pair nets,
we propose a routing method for routing area with obstacles that generates a longer completely parallel dual path. In experiment, the effectiveness of our proposed method is confirmed.
Keyword (in Japanese) (See Japanese page) 
(in English) specified length routing / parallel wire / maximum wire length / PCB / amount of delay / / /  
Reference Info. IEICE Tech. Rep., vol. 108, no. 478, VLD2008-136, pp. 59-64, March 2009.
Paper # VLD2008-136 
Date of Issue 2009-03-04 (VLD) 
ISSN Print edition: ISSN 0913-5685  Online edition: ISSN 2432-6380
Copyright
and
reproduction
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF VLD2008-136

Conference Information
Committee VLD  
Conference Date 2009-03-11 - 2009-03-13 
Place (in Japanese) (See Japanese page) 
Place (in English)  
Topics (in Japanese) (See Japanese page) 
Topics (in English) Design Technology for a System-on-Silicon 
Paper Information
Registration To VLD 
Conference Code 2009-03-VLD 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) A Maximization Method of Parallel Wire Lengths in Routing Area With Lengths in Routing Area with Obstacles 
Sub Title (in English)  
Keyword(1) specified length routing  
Keyword(2) parallel wire  
Keyword(3) maximum wire length  
Keyword(4) PCB  
Keyword(5) amount of delay  
Keyword(6)  
Keyword(7)  
Keyword(8)  
1st Author's Name Suguru Suehiro  
1st Author's Affiliation Tokyo Institute of Technology (Tokyo Inst. of Tech.)
2nd Author's Name Yukihide Kohira  
2nd Author's Affiliation Tokyo Institute of Technology (Tokyo Inst. of Tech.)
3rd Author's Name Atsushi Takahashi  
3rd Author's Affiliation Tokyo Institute of Technology (Tokyo Inst. of Tech.)
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Speaker
Date Time 2009-03-11 16:40:00 
Presentation Time 25 
Registration for VLD 
Paper # IEICE-VLD2008-136 
Volume (vol) IEICE-108 
Number (no) no.478 
Page pp.59-64 
#Pages IEICE-6 
Date of Issue IEICE-VLD-2009-03-04 


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