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Paper Abstract and Keywords
Presentation 2009-03-11 15:50
A Lower Cost Clock Tree Synthesis Method in General-Synchronous Framework using an EDA tool
Hiroyoshi Hashimoto, Yukihide Kohira, Atsushi Takahashi (Tokyo Inst. of Tech.) VLD2008-134
Abstract (in Japanese) (See Japanese page) 
(in English) Clock trees for general synchronous framework can be synthesized by using a clock tree synthesis (CTS) engine in EDA system. However, the cost of a synthesized clock tree tends to be large and is not acceptable in most cases in design scene. In this paper, we propose a practical clock tree synthesis method using a CTS engine in EDA system. In our proposed method, the clock input timing of each FF which is given to the CTS engine as a target is set so that the cost of clock tree synthesized by the CTS engine is small. In experiments, it is confirmed that the cost of the clock tree synthesized by our method is small enough and the clock tree enables enough circuit performance.
Keyword (in Japanese) (See Japanese page) 
(in English) general synchronous / clock schedule / cluster / clock tree synthesis / EDA / / /  
Reference Info. IEICE Tech. Rep., vol. 108, no. 478, VLD2008-134, pp. 47-52, March 2009.
Paper # VLD2008-134 
Date of Issue 2009-03-04 (VLD) 
ISSN Print edition: ISSN 0913-5685  Online edition: ISSN 2432-6380
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Download PDF VLD2008-134

Conference Information
Committee VLD  
Conference Date 2009-03-11 - 2009-03-13 
Place (in Japanese) (See Japanese page) 
Place (in English)  
Topics (in Japanese) (See Japanese page) 
Topics (in English) Design Technology for a System-on-Silicon 
Paper Information
Registration To VLD 
Conference Code 2009-03-VLD 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) A Lower Cost Clock Tree Synthesis Method in General-Synchronous Framework using an EDA tool 
Sub Title (in English)  
Keyword(1) general synchronous  
Keyword(2) clock schedule  
Keyword(3) cluster  
Keyword(4) clock tree synthesis  
Keyword(5) EDA  
1st Author's Name Hiroyoshi Hashimoto  
1st Author's Affiliation Tokyo Institute of Technology (Tokyo Inst. of Tech.)
2nd Author's Name Yukihide Kohira  
2nd Author's Affiliation Tokyo Institute of Technology (Tokyo Inst. of Tech.)
3rd Author's Name Atsushi Takahashi  
3rd Author's Affiliation Tokyo Institute of Technology (Tokyo Inst. of Tech.)
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Date Time 2009-03-11 15:50:00 
Presentation Time 25 
Registration for VLD 
Paper # IEICE-VLD2008-134 
Volume (vol) IEICE-108 
Number (no) no.478 
Page pp.47-52 
#Pages IEICE-6 
Date of Issue IEICE-VLD-2009-03-04 

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