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Paper Abstract and Keywords
Presentation 2009-03-11 14:00
Adjustable Safe Clocking and Relevant Register Assignment in Datapath Synthesis
Keisuke Inoue, Mineo Kaneko, Tsuyoshi Iwagaki (JAIST) VLD2008-130
Abstract (in Japanese) (See Japanese page) 
(in English) With the advance of process technology, delay variations have become a serious problem. Recently, the register assignment based on Backward-Data-Direction (BDD) clocking technique in datapath synthesis has been proposed for ensuring the hold timing constraints under delay variations. A major drawback of this datapath, it tends to increase the number of registers. In this paper, we consider the problem using BDD clocking which can be changed the direction with each control step, named adjustable clocking. In this case, we show a polynomial time algorithm to
solve the register minimization problem, and the number of required registers are equal to the number of maximum data life-time overlaps with the addition of at most one register.
Keyword (in Japanese) (See Japanese page) 
(in English) Datapath synthesis / delay variation / hold timing constraint / adjustable clocking / / / /  
Reference Info. IEICE Tech. Rep., vol. 108, no. 478, VLD2008-130, pp. 23-28, March 2009.
Paper # VLD2008-130 
Date of Issue 2009-03-04 (VLD) 
ISSN Print edition: ISSN 0913-5685  Online edition: ISSN 2432-6380
Copyright
and
reproduction
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
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Conference Information
Committee VLD  
Conference Date 2009-03-11 - 2009-03-13 
Place (in Japanese) (See Japanese page) 
Place (in English)  
Topics (in Japanese) (See Japanese page) 
Topics (in English) Design Technology for a System-on-Silicon 
Paper Information
Registration To VLD 
Conference Code 2009-03-VLD 
Language English (Japanese title is available) 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) Adjustable Safe Clocking and Relevant Register Assignment in Datapath Synthesis 
Sub Title (in English)  
Keyword(1) Datapath synthesis  
Keyword(2) delay variation  
Keyword(3) hold timing constraint  
Keyword(4) adjustable clocking  
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1st Author's Name Keisuke Inoue  
1st Author's Affiliation Japan Advanced Institute of Science and Technology (JAIST)
2nd Author's Name Mineo Kaneko  
2nd Author's Affiliation Japan Advanced Institute of Science and Technology (JAIST)
3rd Author's Name Tsuyoshi Iwagaki  
3rd Author's Affiliation Japan Advanced Institute of Science and Technology (JAIST)
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Speaker
Date Time 2009-03-11 14:00:00 
Presentation Time 25 
Registration for VLD 
Paper # IEICE-VLD2008-130 
Volume (vol) IEICE-108 
Number (no) no.478 
Page pp.23-28 
#Pages IEICE-6 
Date of Issue IEICE-VLD-2009-03-04 


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