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Paper Abstract and Keywords
Presentation 2009-03-11 10:30
Optimum Code Scheduling for VLIW DSP SPXK5 considering Conditional Execution
Tetsuya Yamamoto, Nagisa Ishiura (Kwansei Gakuin Univ.), Takahiro Kumura, Masao Ikekawa (NEC), Masaharu Imai (Osaka Univ.) VLD2008-126
Abstract (in Japanese) (See Japanese page) 
(in English) This article presents an optimum code scheduling method for digital signal processor SPXK5 taking account of its architectural details and
conditional execution. SPXK5 is a VLIW (very long instruction word) processor dedicated for digital signal processing application which
can execute up to four operations per execution packet.
The proposed scheduling method takes a DFG (dataflow graph) representing a basic block as input and attempts to finds the optimum code,
in terms of the execution cycles, by solving 0-1 integer linear programming taking all the architectural issues into account such as the structural constraints regarding the pipeline, the size of the execution packet, the capacity of the register files, etc.
It also exploits grouping/ungrouping and exclusiveness of predicated operations to optimize the code.
In a preliminary experiment an implemented scheduler using a pseudo Boolean satisfiability solver PBS successfully
found the optimum scheduling for DFGs with about 20 operations within a feasible CPU time.
Keyword (in Japanese) (See Japanese page) 
(in English) VLIW DSP / SPXK5 / code scheduling / code optimization / condition execution / / /  
Reference Info. IEICE Tech. Rep., vol. 108, no. 478, VLD2008-126, pp. 1-6, March 2009.
Paper # VLD2008-126 
Date of Issue 2009-03-04 (VLD) 
ISSN Print edition: ISSN 0913-5685  Online edition: ISSN 2432-6380
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF VLD2008-126

Conference Information
Committee VLD  
Conference Date 2009-03-11 - 2009-03-13 
Place (in Japanese) (See Japanese page) 
Place (in English)  
Topics (in Japanese) (See Japanese page) 
Topics (in English) Design Technology for a System-on-Silicon 
Paper Information
Registration To VLD 
Conference Code 2009-03-VLD 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) Optimum Code Scheduling for VLIW DSP SPXK5 considering Conditional Execution 
Sub Title (in English)  
Keyword(1) VLIW DSP  
Keyword(2) SPXK5  
Keyword(3) code scheduling  
Keyword(4) code optimization  
Keyword(5) condition execution  
1st Author's Name Tetsuya Yamamoto  
1st Author's Affiliation Kwansei Gakuin University (Kwansei Gakuin Univ.)
2nd Author's Name Nagisa Ishiura  
2nd Author's Affiliation Kwansei Gakuin University (Kwansei Gakuin Univ.)
3rd Author's Name Takahiro Kumura  
3rd Author's Affiliation NEC Corporation (NEC)
4th Author's Name Masao Ikekawa  
4th Author's Affiliation NEC Corporation (NEC)
5th Author's Name Masaharu Imai  
5th Author's Affiliation Osaka University (Osaka Univ.)
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Date Time 2009-03-11 10:30:00 
Presentation Time 25 
Registration for VLD 
Paper # IEICE-VLD2008-126 
Volume (vol) IEICE-108 
Number (no) no.478 
Page pp.1-6 
#Pages IEICE-6 
Date of Issue IEICE-VLD-2009-03-04 

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