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| Presentation | 2009-03-10 14:15 Hardware Implementations of the Cryptographic Hash Function Familiy AURORA Toru Akishita (Sony), Tadaoki Yamamoto, Hiroyuki Abe (Sony LSI Design)  IT2008-88 ISEC2008-146 WBS2008-101 |
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| Abstract | (in Japanese) | (See Japanese page) |
| (in English) | This paper presents optimization techniques and evaluation results in hardware implementations of the hash function family AURORA. Each component in $F$-functions of AURORA can be implemented efficiently in hardware, and its design enables a variety of implementations, from high-speed to area-restricted implementations. In our evaluations using a 0.13 $\mu {\rm m}$ CMOS ASIC library, AURORA-256 achieves the highest throughput of 10.4 Gbps with area of 35.0 Kgate in a speed-optimized implementation, and the smallest area of 8.9 Kgate with throughput of 1.1 Gbps in an area-optimized implementation. AURORA-512 achieves the highest throughput of 9.1 Gbps in a speed-optimized implementation, and the smallest area of 12.1 Kgate in an area-optimized implementation. These figures are so advantageous to the best known results of hardware performance of SHA-2 that AURORA is a highly efficient hash function family in hardware implementation. |
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| Keyword | (in Japanese) | (See Japanese page) |
| (in English) | hash function / AURORA / hardware implementation / / / / / | |
| Reference Info. | IEICE Tech. Rep., vol. 108, no. 473, ISEC2008-146, pp. 287-294, March 2009. | |
| Paper # | ISEC2008-146 | |
| Date of Issue | 2009-03-02 (IT, ISEC, WBS) | |
| ISSN | Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 | |
| Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) | |
| Download PDF | IT2008-88 ISEC2008-146 WBS2008-101 |
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| Conference Information | |
| Committee | WBS IT ISEC |
| Conference Date | 2009-03-09 - 2009-03-10 |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | Hakodate Mirai Univ. |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
| Paper Information | |
| Registration To | ISEC |
| Conference Code | 2009-03-WBS-IT-ISEC |
| Language | Japanese |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Hardware Implementations of the Cryptographic Hash Function Familiy AURORA |
| Sub Title (in English) | |
| Keyword(1) | hash function |
| Keyword(2) | AURORA |
| Keyword(3) | hardware implementation |
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| 1st Author's Name | Toru Akishita |
| 1st Author's Affiliation | Sony Corporation (Sony) |
| 2nd Author's Name | Tadaoki Yamamoto |
| 2nd Author's Affiliation | Sony LSI Design Inc. (Sony LSI Design) |
| 3rd Author's Name | Hiroyuki Abe |
| 3rd Author's Affiliation | Sony LSI Design Inc. (Sony LSI Design) |
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| Speaker | Author-1 |
| Date Time | 2009-03-10 14:15:00 |
| Presentation Time | 25 minutes |
| Registration for | ISEC |
| Paper # | IT2008-88, ISEC2008-146, WBS2008-101 |
| Volume (vol) | vol.108 |
| Number (no) | no.472(IT), no.473(ISEC), no.474(WBS) |
| Page | pp.287-294 |
| #Pages | 8 |
| Date of Issue | 2009-03-02 (IT, ISEC, WBS) |
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